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d a t a sh eet product speci?cation supersedes data of 2001 mar 07 file under integrated circuits, ic17 2001 apr 17 integrated circuits pcd6003 digital telephone answering machine chip
2001 apr 17 2 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 contents 1 features 2 application summary 2.1 metalink emulation 3 general description 4 ordering information 5 block diagram 6 pinning information 6.1 pinning 6.2 pin description 6.3 pin types 7 functional description 7.1 architecture 7.2 i/o summary 7.3 overview of functional description 8 power supply, reset and start-up 8.1 power supply 8.2 reset and start-up 9 ticb - generation and selection of system clocks 9.1 microprocessor, dsp, codec and iom clock generation 9.2 system clocks 9.3 real-time clock generation 10 the microcontroller 10.1 microcontroller architecture 10.2 memory mapping 10.3 sfr mapping 10.4 microcontroller interrupts 10.5 interface to dsp 10.6 interface to real-time clock (rtc) 10.7 interface to the memory control block (mcb) 10.8 the test registers cdtrx, pmtrx and tctrl 10.9 interface to timing and control block (ticb) 10.10 power and interrupt control register (pcon) 10.11 i 2 c-bus 10.12 msk modem 10.13 le control 11 dsp i/o registers 11.1 interface to codec 12 external memory interface 12.1 supported flash memories 12.2 dtam external interface during target debugging 13 the codecs 13.1 definitions 13.2 codec architecture 14 analog voltage reference (avr) 14.1 bandgap reference 14.2 analog voltage source (avs) 15 iom 15.1 features 15.2 pin description 15.3 functional description 15.4 iom data buffers 15.5 iom control register (iomc) 15.6 timing 16 external i/o interfaces 16.1 external analog interfaces 16.2 external digital interfaces 17 electrical characteristics 17.1 limiting values 17.2 supply characteristics 17.3 digital i/o 17.4 analog supplies and general purpose adc and dac 17.5 codecs 18 application diagrams 19 package outline 20 soldering 20.1 introduction to soldering surface mount packages 20.2 reflow soldering 20.3 wave soldering 20.4 manual soldering 20.5 suitability of surface mount ic packages for wave and reflow soldering methods 21 data sheet status 22 definitions 23 disclaimers 24 purchase of philips i 2 c components
2001 apr 17 3 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 1 features excellent speech quality at average: 2.6, 3.2 or 5.2 kbits/s harmony or fixed 16.0 kbits/s p 2 cm compression rate high quality music transparent encoding with 16.0 kbits/s p 2 cm excellent background noise suppression (bns) algorithm for speech quality improvement through recording with reduced background noise (available with p 2 cm and harmony encoding) speech compression rate selection: 2.6, 3.2 or 5.2 kbits/s harmony, 16.0 kbits/s p 2 cm speech decompression rate selection: 2.6, 3.2 or 5.2 kbits/s, 16.0 kbits/s p 2 cm variable playback speed: 50%, 100% and 200% of real time voice prompt playback philips international language library (pill) support tools available; coding at 2.6, 3.2 or 5.2 kbits/s voice operated start message recording (vox) call progress detection by busy tone detection and programmable silence detection recording time of minimum 20 minutes in 4-mbit flash memory (at 3.2 kbits/s) excellent true full-duplex handsfree performance provided by philips phlux algorithm on-hook caller id detection according to bell 202 and v.23 standards, as well as dtmf caller id support caller alerting signal (cas) - caller id level 2 dual tone generation for dtmf, melody tones and information tones optional dial tone detection, and optional ringing detection using hardware caller identification (cid) interface dtmf detection (for remote control function) with local echo canceller for high reliability digital volume control mixed digital/analog adaptive limit and/or level control of audio input signals programmable analog codec gain for easy interfacing internal 80c51 microcontroller can operate as system controller; with selectable operating frequencies between 1 and 21 mhz internal 80c51 microcontroller emergency operation down to 2.2 v eliminates the need for external diallers in telephone answering machine applications standard 80c51 development tools allow fast design of man-machine-interface (mmi) features on-board minimum shift keying (msk) modem for ct0/ct1 applications two integrated differential bit stream analog-to-digital converters (adcs) for high quality audio input two integrated differential bitstream digital-to-analog converters (dacs) for high quality audio output software selectable auxiliary codec input channel up to 38 general purpose digital i/o lines (most of them bidirectional) including i 2 c-bus, available for connection to keyboard, display, line interface, etc. on-chip 2-channel time multiplexed 8-bit general purpose adc for e.g. parallel set detection and battery voltage measurement on-chip 8-bit general purpose dac for e.g. speaker amplifier volume control day and time stamp possibility using built-in real-time clock flexible speech memory interface for connection of several types of speech flash memory (serial, cad or parallel) and dram i 2 c master/slave bus for peripheral control or i 2 c-bus speech memory access extensive power management support for battery and emergency operation, also allowing portable (voice memo) applications digital iom a/u-law interface for slave or master mode operation at various bit rates emergency operation from telephone line power only; microprocessor and dtmf generator continue to operate in this mode on-chip software switchable supply voltage for electret microphone single low supply voltage (2.2 to 2.8 v) built-in single low-frequency, low-power, crystal or ceramic resonator oscillator and on-chip pll to reduce emi stand-alone operation with low cost pal, ntsc and dtmf crystals
2001 apr 17 4 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 api providing flash memory management functions such as speech, telephone or cid data storage pin and software compatible with the pcd6002 otp-device (see application note for restrictions). 2 application summary the pcd6003 can be used in various applications, some of which are listed below. refer to chapter 18 for the corresponding outline application diagrams. stand-alone digital answering machine; with handsfree feature phone with integrated digital answering machine and full-duplex handsfree with excellent bns dual-line digital answering machines multi-party conference call applications multi-line answering machine applications analog cordless applications such as ct0/1 base stations; with handsfree and msk modem function for rf digital data transmission portable voice memo recorders automotive applications - car status announcements for example low-cost desktop video conferencing iom master/slave interface to connect directly to digital systems like isdn and dect. 2.1 metalink emulation metalink emulation supported with the standard package. 3 general description the pcd6003 integrates all the digital and analog speech management and processing functions required for a feature-phone with integrated digital answering machine, or a stand-alone digital answering machine into a single low-cost chip. key hardware features which give the chip distinct advantages in performance and application over competitive solutions include: patented high quality 16.0 kbits/s p 2 cm music transparent encoding and decoding with excellent background noise subtraction algorithm the flexibility to change the mmi an easy-to-program standard 80c51 microcontroller with 32-kbyte internal rom memory high 80c51 microprocessor power for system controller functions of ct0/ct1 system control functions up to 38 general purpose i/o lines for peripheral control i 2 c-bus interface flexible flash memory control to interface to several types of serial and parallel flash memory two integrated 16-bit bitstream audio codecs for true full-duplex handsfree operation or dual-line stand-alone answering machine operation internal digital speech processor (dsp) for excellent harmony sinusoidal speech compression, decompression and variable playback speed embedded dtmf detection, call progress detection, voice operated recording (vox) high quality caller id fsk demodulation and caller alerting signal (cas) detection for cid level 2 two channel telephone line input for caller id fsk and audio interfacing. philips provides a sophisticated api running on the internal 80c51, allowing product developers to design their mmis quickly to suit particular applications. the api takes care of all flash memory and dsp management tasks and can be enhanced on request. for the pre-recorded voice prompts, the philips international language library (pill) tools are available for a standard multimedia pc platform under windows 95/nt. these tools provide a way to compile a range of multi-lingual voice prompts for efficient storage in the speech (flash) memory. the pill tools support various languages and their grammar adaptations. 4 ordering information type number package temperature range ( c) name description version pcd6003h qfp80 plastic quad ?at package; 80 leads (lead length 1.95 mm); body 14 20 2.8 mm sot318-2 - 25 to +70 pcd6003u u/10 sawn wafer on film frame carrier (delivery as known good dies) -- 25 to +70
2001 apr 17 5 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 5 block diagram handbook, full pagewidth mbl269 32 kbyte rom and external interface p4 i 2 c- bus mcb p2 p0 microcontroller 80c51 psen ale, rdn, wrn p4.3 3 2 11 to 4 80 to 73 72 to 65 62 1 64 63 ale ea ma7 to ma0 p2.7 to p2.0 p0.7 to p0.0 p4.3 psen wr rd 55 rstin 54 tst msk iom micm watchdog codec 2 (analog) codec 2 (digital) main and aux ram 56 p4.0/le 57 p4.1/fsk 58 p4.2/fso 59 p4.4/fsi 60 p4.5/gpc p1 14 to 18 p1.0/ex2 to p1.4/ex6 19 p1.5 20 p1.6/scl 21 p1.7/sda 52 p3.7/ min/ di ma p3 51 p3.6/ mout2/ fsc 50 p3.5/ t1 49 p3.4/ t0 48 p3.3/ ex1n 47 p3.2/ ex0n 46 p3.1/ mout1/ dck 45 26 spkrm 24 micp 25 v mic analog voltage reference and supply 27 v bgp 29 v ref 30 daout general purpose a/d and d/a 33 ad1in 32 ad0in 31 spkrp 23 lifmin2 codec 1 (analog) codec 1 (digital) 36 lifpin 35 lifmin1 37 lifpout 39 lifmout 38 p3.0/ mout0/ do xtal1 oscillator and pll ticb pcd6003 idle events m c_clk dmi rstana clk main bus wake-up dspclk dsp plus rom, ram 42 xtal2 41 v ssa v sspll wake-up 28 v dda v ddpll 34 43 40 53 12 44 v ss3v1 v dd3v1 v ss3v2 v dd3v2 13 61 22 v ss3v3 v dd3v3 fig.1 block diagram.
2001 apr 17 6 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 6 pinning information 6.1 pinning handbook, full pagewidth pcd6003 mbl270 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 64 63 62 61 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p4.5/gpc p4.4/fsi p4.2/fso p4.1/fsk p4.0/le wr rd p4.3 v ss3v2 rstin tst v dd3v1 p3.7/min/di p3.6/mout2/fsc p3.5/t1 p3.4/t0 p3.3/ex1n p3.2/ex0n p3.1/mout1/dck p3.0/mout0/do v dd3v3 v ddpll xtal1 xtal2 ma1 ma2 ma3 ma4 ma5 psen ea ale ma0 ma6 ma7 v dd3v2 v ss3v1 p1.0/ex2 p1.1/ex3 p1.2/ex4 p1.3/ex5 p1.4/ex6 p1.5 p1.6/scl p1.7/sda v ss3v3 spkrp spkrm 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 micp micm v mic v ssa v bgp v ref ad0in ad1in daout v dda lifpin lifmin2 lifmin1 lifmout lifpout v sspll p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 fig.2 pin configuration.
2001 apr 17 7 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 6.2 pin description table 1 qfp80 package symbol pin i/o reset state pin type (1) description psen 1 o h ucp4mthuwh program store enable (80c51) ea 2 i z ucp4mthuwh external access not (80c51) ale 3 o h ucp4mthuwh address latch enable signal (80c51) ma0 4 o l ops10c general purpose output; ea = 1; add_low; ea = 0 ma1 5 o l ops10c general purpose output; ea = 1; add_low; ea = 0 ma2 6 o l ops10c general purpose output; ea = 1; add_low; ea = 0 ma3 7 o l ops10c general purpose output; ea = 1; add_low; ea = 0 ma4 8 o l ops10c general purpose output; ea = 1; add_low; ea = 0 ma5 9 o l ops10c general purpose output; ea = 1; add_low; ea = 0 ma6 10 o l ops10c general purpose output; ea = 1; add_low; ea = 0 ma7 11 o l ops10c general purpose output; ea = 1; add_low; ea = 0 v dd3v2 12 power supply positive supply 2 (3.0 v) for digital circuitry v ss3v1 13 power supply ground supply 1 for digital circuitry p1.0/ex2 14 i/o h ucp4mthuwh 80c51 port pin/ex2 input p1.1/ex3 15 i/o h ucp4mthuwh 80c51 port pin/ex3 input p1.2/ex4 16 i/o h ucp4mthuwh 80c51 port pin/ex4 input p1.3/ex5 17 i/o h ucp4mthuwh 80c51 port pin/ex5 input p1.4/ex6 18 i/o h ucp4mthuwh 80c51 port pin/ex6 input p1.5 19 i/o h ucp4mthuwh 80c51 port pin p1.6/scl 20 i/o z i 2 c400k 80c51 port pin/i 2 c-bus clock p1.7/sda 21 i/o z i 2 c400k 80c51 port pin/i 2 c-bus data v ss3v3 22 power supply ground supply 3 for digital circuitry spkrp 23 o z ana positive output to speaker from codec2 (handsfree) spkrm 24 o z ana negative output to speaker from codec2 (handsfree) micp 25 i 0.625 v ana positive input from microphone to codec2 (handsfree) micm 26 i 0.625 v ana negative input from microphone to codec2 (handsfree) v mic 27 o z ana positive microphone supply voltage (2 v) v ssa 28 power supply ground supply voltage for analog circuits v bgp 29 o 1.25 v band gap output voltage (v bgp ) v ref 30 o 2.00 v ana reference voltage (v ref ) ad0in 31 i - ana analog input channel 1 for general purpose adc ad1in 32 i - ana analog input channel 2 for general purpose adc daout 33 o 0.5v dda ana analog output channel for general purpose d/a converter v dda 34 power supply positive supply (2.5 v) for analog circuits lifpin 35 i 0.625 v ana positive analog input of codec1 (line codec) lifmin2 36 i 0.625 v ana negative analog input 2 of codec1 (line codec) lifmin1 37 i 0.625 v ana negative analog input 1 of codec1 (line codec) lifmout 38 o z ana negative analog output of codec1 (line codec)
2001 apr 17 8 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 lifpout 39 o z ana positive analog output of codec1 (line codec) v sspll 40 power supply ground supply for xtal clock and pll circuitry xtal2 41 o running ana crystal oscillator output xtal1 42 i - ana crystal oscillator input v ddpll 43 power supply positive supply (2.5 v) for xtal clock and pll circuitry v dd3v3 44 power supply positive supply 3 (3.0 v) for digital circuitry p3.0/mout0/do 45 i/o h ucp4mthuwh 80c51 port pin/msk output 0/iom data output p3.1/mout/dck 46 i/o h ucp4mthuwh 80c51 port pin/msk output 1/iom dck signal p3.2/ex0n 47 i/o h ucp4mthuwh 80c51 port pin/ex0n input p3.3/ex1n 48 i/o h ucp4mthuwh 80c51 port pin/ex1n input p3.4/t0 49 i/o h ucp4mthuwh 80c51 port pin/timer 0 input p3.5/t1 50 i/o h ucp4mthuwh 80c51 port pin/timer 1 input p3.6/mout2/fsc 51 i/o h ucp4mthuwh 80c51 port pin/msk output 2/iom fsc signal p3.7/min/di 52 i/o h ucp4mthuwh 80c51 port pin/msk input/iom data input v dd3v1 53 power supply positive supply 1 (2.5 v) for digital circuitry tst 54 i - iptd test input (recommended to be connected to ground) rstin 55 i - ipth reset in p4.0/le 56 i/o l ucp4mthuwh general purpose i/o/lcd enable, con?gured as od after reset p4.1/fsk 57 i/o z ucp4mthuwh general purpose i/o/flash serial clock, con?gured as od after reset p4.2/fso 58 i/o z ucp4mthuwh general purpose i/o/flash serial out, con?gured as od after reset p4.4/fsi 59 i/o z ucp4mthuwh general purpose i/o/flash serial in, con?gured as od after reset p4.5/gpc 60 i/o l ucp4mthuwh general purpose i/o/gp clock output (crystal clock or microcontroller clock), con?gured as od after reset v ss3v2 61 power supply negative supply 2 (ground) for digital circuitry p4.3 62 i/o z ucp4mthuwh general purpose i/o, con?gured as od after reset rd 63 o z ucp4mthuwh 80c51 read not, con?gured as od after reset wr 64 o z ucp4mthuwh 80c51 write not, con?gured as od after reset p0.0 65 i/o z uceda4mtuwh 80c51 port 0 input/output p0.1 66 i/o z uceda4mtuwh 80c51 port 0 input/output p0.2 67 i/o z uceda4mtuwh 80c51 port 0 input/output p0.3 68 i/o z uceda4mtuwh 80c51 port 0 input/output p0.4 69 i/o z uceda4mtuwh 80c51 port 0 input/output p0.5 70 i/o z uceda4mtuwh 80c51 port 0 input/output p0.6 71 i/o z uceda4mtuwh 80c51 port 0 input/output p0.7 72 i/o z uceda4mtuwh 80c51 port 0 input/output p2.0 73 o l ucp4mthuwh general purpose output, ea = 1; add_high; ea = 0 p2.1 74 o l ucp4mthuwh general purpose output, ea = 1; add_high; ea = 0 symbol pin i/o reset state pin type (1) description
2001 apr 17 9 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 note 1. the pin type codes are explained in section 6.3. p2.2 75 o l ucp4mthuwh general purpose output, ea = 1; add_high; ea = 0 p2.3 76 o l ucp4mthuwh general purpose output, ea = 1; add_high; ea = 0 p2.4 77 o l ucp4mthuwh general purpose output, ea = 1; add_high; ea = 0 p2.5 78 o l ucp4mthuwh general purpose output, ea = 1; add_high; ea = 0 p2.6 79 o l ucp4mthuwh general purpose output, ea = 1; add_high; ea = 0 p2.7 80 o l ucp4mthuwh general purpose output, ea = 1; add_high; ea = 0 symbol pin i/o reset state pin type (1) description 6.3 pin types 6.3.1 p ower supply pins there are 6 different power supply domains (see fig.3): digital core circuit (2.5 v): v dd3v1 /v ss3v1 digital periphery circuit (3.0 v): v dd3v2 /v ss3v2 and v dd3v3 /v ss3v3 pll circuits and crystal oscillator (2.5 v): v ddpll and v sspll analog circuits (2.5 v): v dda and v ssa . all v ss pins must be connected to the same ground plane on the printed-circuit board (pcb). all 2.5 v v dd pins must be connected to the same power supply. all v dd pins have to be separately decoupled, according to chapter 18. 6.3.2 a nalog pins ana: full esd protected analog i/o pad (double protection diode). 6.3.3 d igital pins ucp4mthuwh: 4 ma 80c51 i/o pins uceda4mtuwh: 4 ma 80c51 i/o pins with input enable iptd: input pad buffer; pull-down ipth: input pad buffer with schmitt trigger ops10c: output pad; push-pull; 4 ma output drive; 10 ns slew control i 2 c400k: bidirectional open-drain i 2 c-bus compatible pad. handbook, halfpage mgt429 v dd3v1 v ss3v1 v dd3v2 v ss3v2 v dd3v3 v ss3v3 v ddpll v sspll v dda v ssa fig.3 pcd6003 chip supply rails with protection diodes.
2001 apr 17 10 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 7 functional description 7.1 architecture the pcd6003 architecture is based on an embedded 8-bit 80c51 microcontroller, a philips real dsp core, two high quality ad/da codecs and a 32-kbyte rom microcontroller memory. refer to the block diagram in chapter 5. the most important dsp peripherals are the: codecs dsp program rom dsp ram iom interface. the most important microcontroller peripherals are the: memory control block (mcb) watchdog timer general purpose ports i 2 c-bus interface msk block (used for digital data transfer and analogue cordless applications). the mcb, through ports p0, p2, p4 and memory address (ma) can interface to various types of flash memory including serial, parallel or multiplexed command/address/data. most of the peripherals are controlled via microcontroller special function registers. the microcontroller initializes and controls the: dsp via the dsp to microcontroller interface (dmi) speech flash memory via the memory control block (mcb), and p0/p4 port pins clock and power settings via the timing and control block (ticb) analog section via its special function registers (sfr). 7.2 i/o summary all digital i/o for peripherals such as keyboard, display, line interface and others are handled by the microcontroller via ports p0, p1, p2, p3, p4, and ma. port 2 and ma provide 16 general purpose output-only lines (not bit-addressable, push-pull, 4 ma) to drive peripherals. these ports can be used for peripheral control if ea is logic 1. the 4 ma driving level should be adequate to drive a low power led directly if required. in addition to these 16 output-only lines, 16 general purpose i/o lines are provided by ports 1 and 3. port 1 can handle 5 external interrupts (p1.0 to p1.4) that are also high/low interrupt level programmable. port 1 also contains the i 2 c-bus. port 3 can handle an additional 2 external interrupts (p3.2 and p3.3) which are active low only. the timer 0 and timer 1 inputs are available on port 3 as for the standard 80c51. ports 1 and 3 are 80c51 weak pull-up i/o lines with a 4 ma sink capability, with the exception of the i 2 c-bus lines p1.6 and p1.7 which are open-drain. if the p3 alternate port function for the msk modem is chosen then the standard i/o is not available on pins p3.0, p3.1, p3.6 and p3.7. port 4 lines are 6 more general purpose i/o. they will be configured as open-drain after reset. these open-drains can be connected via pull-up resistors to the telephone system supply or to the mains ac supply. if a flash memory with a different supply voltage (v dd_flash up to 3.3 v) is connected, p4.3 can be pulled-up to this voltage. this is required such that the chip enable not (cen) input of a flash device is equal to v dd_flash to reduce the standby power consumption. all other port 4 pins should not be pulled up to a voltage higher than v dd_dtam . in case a cad flash is used, p4.4 and p4.5 are free bit-addressable ports. all p4 pins also can be configured to push-pull via the register p4cfg. this brings the total of i/o lines to 38 (of which 16 are output only). in case an i 2 c-bus lcd driver is used, p4.0, at which a latch enable (le) function is provided for 68xxx family microcontroller peripherals, is an additional free bit-addressable open-drain i/o port. the analog interfacing for the pcd6003 consists of the analog audio i/o of the 2 codecs and 2 additional general purpose analog-to-digital inputs and a general purpose digital-to-analog output for voltage measurement and control respectively. furthermore a stabilized microphone supply output v mic is provided which can be switched on/off for power control. one audio codec is dedicated for the pstn line communication (codec1). this line codec has a differential low ohmic analog output which consists of lifpout and lifmout. in case only one of the differential outputs is used, lifpout should be chosen, since the emergency mode dtmf signal is also available.
2001 apr 17 11 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 the line codec has 3 inputs which are configurable as 2 single-ended inputs lifmin1 and lifmin2 that can be selected by software control, while lifpin is ac coupled to ground. it is also possible to use one of the lifmin inputs (leaving the other unconnected) in conjunction with the lifpin input as a differential input, in case a high cmrr is required. the second codec is dedicated for a local microphone and loudspeaker connection (codec2). this handsfree codec has a differential low ohmic analog output which consists of spkrp and spkrm. this output can be used either differential or single ended. the speaker output impedance and driving level is not suitable to directly connect a speaker. the handsfree codec has a differential microphone input which consists of micp and micm. this differential input features a fixed 16 db microphone preamplifier. both the line and handsfree codec outputs have on-chip filtering for out of band signals such that no external filters are required. there are 2 8-bit analog-to-digital inputs ad0in and ad1in for voltage measurements which can be used for parallel set detection algorithms or battery control. an 8-bit dac output daout can provide an analog peripheral control signal. 7.3 overview of functional description the detailed functional description is divided into separate chapters covering the major functional blocks, as follows: chapter 8 power supply, reset and start-up chapter 9 ticb - generation and selection of system clocks chapter 10 the microcontroller chapter 11 dsp i/o registers chapter 12 external memory interface chapter 13 the codecs chapter 16 external i/o interfaces. 8 power supply, reset and start-up 8.1 power supply the pcd6003 core circuitry is supplied by three 3 v supply pairs. the crystal oscillator and pll are supplied with a separate pair of supply pins to provide a clean supply voltage required for low jitter. the following supplies exist: v dd3v1 and v ss3v1 : digital core supply 1 (2.5 v) v dd3v2 and v ss3v2 : digital supply 2 (3.0 v) v dd3v3 and v ss3v3 : digital supply 3 (3.0 v) v dda and v ssa : analog supply (2.5 v) v ddpll and v sspll : crystal clock and pll supply (2.5 v). 8.2 reset and start-up after applying the power supply voltage, the chip will need an external power-on reset via pin rstin. rstin should remain active (logic 1) until v trh and has to become active again before the power supply drops below v trl . the reset via rstin is one of 3 possible ways to perform a reset. the following reset conditions exist: wake-up from system off (crystal is off, but power is on) by an external interrupt rstin, reset in from pin rstin watchdog timer expires. after a power-on reset and after a wake-up from system off, a counter is activated, which guarantees that the first instruction fetch of the microcontroller is delayed by at least 4096 clock cycles. to reduce power consumption during reset, the following reset strategy is used. if the dsp function is not required, it can be switched off by the microcontroller. the dsp reset will then be delayed (until it is switched on again), in order to avoid a large (reset) power consumption.
2001 apr 17 12 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 9 ticb - generation and selection of system clocks the ticb generates the clocks for all digital chip blocks, and controls the on/off switching of these blocks by using clock gating. the ticb is controlled via the microcontroller sfr registers symod, ckcon and spcon. the ticb contains: an input section to adapt to different input clock rates a clock generation section a clock selection section the real-time clock for a 1 minute interrupt generation the microcontroller interrupt timers (fs_event and time_event) and the dsp interrupt timer (fs1) to respectively synchronize the microcontroller and dsp processes. 9.1 microprocessor, dsp, codec and iom clock generation figure 4 shows the ticb input section and the clock generation section. the clock generation section contains a pll to generate the clock rates which are higher then the input clock rate. with the input section, a wider variety of input clock frequencies can be adapted to the input frequency values needed by the pll (3.456 or 3.580 mhz). in order to save power the pll can be switched off. this should however only be done when the chip is in the emergency mode. when switching on the pll, it takes 40 m s (173 emergency clock periods) until the clock frequencies are derived from the pll output. table 2 gives a description of the signals and their values for a crystal frequency of 3.456 and 3.580 mhz. the clock generation section also contains logic to synchronize the codec timing signals and the dsp and microcontroller interrupt timers to an external frame sync. (fsc). this synchronization is only activated when using the iom in slave mode. if the iom is activated in master mode, the ticb generates the dck and fsc signals from clk28. some of the clock signals can be made available as general purpose clock, for various peripherals needing a clock source such as an pca1070 line interface. this general purpose clock (gpc) signal is an alternative output of p4.5 and can be turned on with altp bit 3. with altp bit 2, the source for gpc can be defined. the gpc source is emg_clk (normally 3.58 mhz) when bit 2 is logic 0 and the gpc source is m c_clk when bit 2 is set to logic 1. as a spike-free gpc is not guaranteed when switching between these clocks, it is recommended to first set the clock source before switching on the gpc. the altp register is described in more detail in section 16.2.
2001 apr 17 13 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 handbook, full pagewidth mgt430 2 2 6 24 3 4 192 dck generator clk3gen control and synchronization codec timing signals clk_21 clk_3 cdccntrl emg_clk pll 24 on clk_in symod [ 5 ] pll_on clk_28 clk_21 clk_14 0 1 clk_7 clk_1 clk3_emg fsc dck clk_3 fs1 2 clk_42 2 4 symod [ 5 ] pll_on symod[6 or 7] pll_in 20.736 mhz for a 3.456 mhz pll input clock clk3_corr clk3_out ckcon [ 6 or 7 ] fig.4 ticb input section and clock generation.
2001 apr 17 14 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 table 2 descriptions and frequency values for signals shown in fig.4 notes 1. these values are only valid if the rtc mode bit ckcon.6 has been set according to the pll_in frequency used (see also table 6). 2. if the iom slave mode is activated, these clock signals are synchronized to the externally applied fsc. 3. proper iom functionality is only guaranteed at dsp clock frequencies of 28 and 42 mhz. if the iom slave mode is activated, the externally applied dck and fsc signals are used. 4. these master frequencies do not comply to iom specification. for 3.58 mhz crystal operation, proper iom functionality is therefore only guaranteed in master mode. signal function value (mhz) pll_in 3.456 pll_in 3.580 microprocessor and dsp clock signals emg_clk emergency clock 3.456 3.580 clk_42 dsp selectable clock frequency 41.472 42.960 clk_28 dsp selectable clock frequency 27.648 28.640 clk_21 microcontroller selectable clock frequency 20.736 21.480 clk_14 microcontroller selectable clock frequency 13.824 14.320 clk_7 dsp and microcontroller selectable clock frequency 6.912 7.160 clk_1 dsp and microcontroller selectable clock frequency 1.152 1.193 codec clock signals clk_21 input clock for phase corrected clk3_out 20.736 21.480 clk3_emg emg_clk input to clk_3 multiplexer 3.456 3.580 clk3_corr frequency corrected codec clock (24/25 3.58 mhz) - 3.437 (1)(2) clk3_out phase corrected 3.456 mhz codec clock 3.456 (1)(2) - clk14_codec input clock for codecs 13.824 14.320 iom clock/timing signals dckmaster the iom master clock signal dck generated by the ticb 1.536 (1)(3) 1.527 (1)(3)(4) fscmaster the iom master frame sync fsc generated by the ticb 8 khz (1)(3) 7.955 khz (1)(3)(4)
2001 apr 17 15 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 9.2 system clocks figure 5 shows the multiplexers with their input and control signals for the dsp processor clock, the microcontroller clock, the codec clock (clk_3) and the chip input clock frequency. the functional position of the codec clock multiplexer is shown in fig.4. handbook, full pagewidth mgt431 rs q ff clk_3_drt2 clk_3_drt1 clk_3 cdccntrl_clk dsp_idle dsp_wakeup dsp_clk m c_clk dsp_clk_in emg_clk emg_clk emg_clk clk_1 clk_7 clk_14 clk_21 clk_1 clk_7 clk_42 clk_28 clk3_corr clk3_out ckcon [ 2, 3 or 7 ] ckcon [ 4, 5 or 7 ] ckcon [ 6 or 7 ] ckcon [ 0 or 1 ] spcon [ 0 or 1 ] spcon [ 2 or 3 ] spcon[4] 4 2 2 5 fs1 fs_event time_event 3210 fig.5 clock and event rate selection.
2001 apr 17 16 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 9.2.1 s election of system clocks selection of system clocks involves: selection of the crystal input clock in conjunction with pll on/off selection (symod register) selection of clocks for the dsp, microcontroller and codec, together with microcontroller timing interrupt rates (ckcon register) activation, deactivation of individual clocks or deactivation of the whole ticb in order to get an optimum power consumption (spcon register). symod, spcon and ckcon are sfr registers in the digital section which can be directly accessed by the microcontroller. sections 9.2.2 to 9.2.4 summarize the control registers and settings used for system clock selection. the activation of the dsp, and the digital part of both codecs is controlled via the spcon sfr. the clock rates of the dsp and microcontroller, and the microcontroller timing interrupt rates are set via the ckcon sfr. 9.2.2 a nalog s ystem m ode r egister (symod) table 3 analog system mode register (sfr address c5h); reset state 00h 9.2.3 s ystem p ower and c lock c onfiguration r egister (spcon) table 4 system power and clock con?guration register (sfr address 99h); reset state 00h 9.2.4 c lock c ontrol r egister (ckcon) table 5 clock control register (sfr address 9ah); reset state 00h 7654 3 2 10 input clock 1 input clock 0 pll off/on v mic off/on codec2; analog codec1; analog d/a (loudspeaker) off/on a/d (microphone) off/on d/a (to_line) off/on a/d (from_line) off/on 7654 3 2 10 system off spare spare dsp on codec2; digital codec1; digital d/a (loudspeaker) off/on a/d (microphone) off/on d/a (to_line) off/on a/d (from_line) off/on 76543210 emg mode rtc mode dsp clock 1 dsp clock 0 micro clock 1 micro clock 0 fs_event 1 fs_event 0
2001 apr 17 17 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 table 6 shows the input clock selection in the analog section of the chip. note that for 3.456 and 3.58 mhz crystal input clock, no clock division is done prior to inputting it to the pll. after reset the input clock division rate is by default 1. this means that applications using an input clock frequency other than 3.456 or 3.580 mhz, will have to set the proper division rate, after system start-up. otherwise proper functionality of the analog blocks is not guaranteed. table 7 shows the microcontroller clock frequencies. in emergency mode (bit 7 of ckcon reset), the emg_clk is input directly to the microcontroller. the values of ckcon bits 2 and 3 are then irrelevant. note that emergency mode operation is only designed for start-up and pots mode condition. peripheral blocks (such as the codecs and the iom block) are not guaranteed to work when ckcon bit 7 is reset. table 6 input clock selection note 1. the pcd6003 timing system is based on the 3.456 mhz (or multiples) input clock frequency. in order to be able to use the low cost 3.58 mhz crystal or ceramic resonator, a clock frequency correction is needed for some blocks (rtc, codec and iom). iom will only operate in master mode. table 7 microcontroller clock selection notes 1. 6 clocks/cycle. 2. if the pll is switched off when not in emergency mode, the selected clock would not be available. the micro would hang up. before ckcon.7 is set to logic 1, symod.5 must be set to logic 1 to activate the pll. ckcon.6 (rtc mode) symod.7 (input clock 1) symod.6 (input clock 0) input clock division ratio chip input clock frequency (mhz) 0001 3.456 1001 3.580 (1) 0012 6.912 0104 13.824 ckcon.7 (emg mode) ckcon.3 (micro clock 1) ckcon.2 (micro clock 0) symod.5 pll on/off microcontroller clock frequency (1) 0 x x x emg_clk 1 x x 0 do not use (2) 1001 clk_1 1011 clk_7 1101 clk_14 1111 clk_21
2001 apr 17 18 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 table 8 shows the dsp clock frequency settings. setting the dsp frequency to the correct value according to the operation mode of the dsp is done by the application programming interface (api). please refer to the api specification for more details. table 9 shows clk_3 selection (ckcon.6/ckcon.7 according to fig.4). the selection depends on the type of crystal which is connected (determined by rtc mode setting according to table 6). the setting of ckcon [6:7], thus determines the selection of the clk_3 source (see table 2 and fig.4). if ckcon.7 = 0 to denote emergency mode - clk_3 will be derived from the emg_clk, as shown in the following tables. the ticb provides two periodic outputs to the microcontroller: fs_event and time_event. fs_event is programmable to 4 different rates. both outputs are derived from and therefore synchronized to fs1. the outputs are connected to an interrupt input of the microcontroller and called time_event interrupt and fs_event interrupt respectively. the selection of the fs_event interrupt rate is done via the ckcon sfr, see section 9.2.4. figure 8 shows the generation of these interrupts. table 10 shows the selection of the fs_event rate. the fs1 clock is provided by the cdccntrl block shown in fig.4. table 8 dsp clock selection table 9 codec clock selection note 1. a phase corrected clk_3 clock is not available in emergency mode (ckcon.7 = 0). for a clk_3 phase correction (ckcon.6 = 1), clk_21 must be available. table 10 fs_event rate selection ckcon.7 (emg mode) ckcon.5 (dsp clock 1) ckcon.4 (dsp clock 0) symod.5 (pll on/off) dsp clock frequency 0 x x x emg_clk 1 x x 0 no clock active 1001 clk_1 1011 clk_7 1101 clk_42 1111 clk_28 ckcon.7 (emg mode) ckcon.6 (rtc mode) clk_3 source 0 x emg_clk (1) 1 1 clk3_corr 1 0 clk3_out ckcon.1 (fs_event 1) ckcon.0 (fs_event 0) fs_event interrupt rate 0 0 fs1/16 500 hz 2 ms 0 1 fs1/8 1 khz 1 ms 1 0 fs1/4 2 khz 500 m s 1 1 fs1 8 khz 125 m s
2001 apr 17 19 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 9.3 real-time clock generation the real-time clock (rtc) divider provides a 1 minute timing signal which is available as an interrupt to the microcontroller. the rtc_clk input clock is always active, whether the pll is active or not. thus the complete chip can be set into power-down mode (but not system-off mode), where the microcontroller can be woken up by the rtc to maintain the values for date and time. the rtc_clk is directly derived from the emg_clk input clock signal. figure 6 shows the rtc clock generation. to divide a 3.456 or a 3.580 mhz clock into a 1 minute rtc signal a 28 bit counter is required to count 60 3.456 10 6 clock periods. to determine the number of most significant bits of this counter required for an accurate rtc, the maximum allowed time deviation per month and the crystal accuracy need to be taken into account. the lsb of the 28 counter has an accuracy of 1/(60 3.456 10 6 ) = 0.005 parts-per-million (ppm). since a normal crystal accuracy is about 10 ppm it is tolerable to have only the 17 msb of the counter available (10/0.005 = 2000, which implies that the 11 lsb can be disregarded), as shown in fig.6. if one month is set to 30 24 60 60 = 2.6 106 seconds, 10 ppm deviation equals 26 seconds per month or about 5 minutes per year. since there are 2 possible rtc_clk values, 3.580 and 3.456 mhz, there are 2 comparators selectable for the rtc; comp_3.580 and comp_3.456. the nominal value of these comparators are (11 lsb are set to logic 0): comp_3.580: ccd2800h (rtcon = a5h) comp_3.456: c5c1000h (rtcon = 82h). in section 9.2 the conditions for the rtc_mode signal are described.to allow connection of various crystals or ceramic resonators, as well as to provide adjustment of the rtc clock according to the crystal tolerance, 8 of the 17 most significant bits of the comparators are programmable via the sfr register rtcon. the binary values of the comparators are then as shown in table 11. since the accuracy of q11 is 10 ppm, with the adjustment of the rtc via rtcon an accuracy of 5 ppm can be achieved. for an rtc pulse every 1 minute the outer limits of the crystal frequency inputs which can be connected are: comp_3.580 (max): ccff800h ? 3.582600 mhz comp_3.580 (min): cc80000h ? 3.573897 mhz. comp_3.456 (max): c5ff800h ? 3.460267 mhz comp_3.456 (min): c580000h ? 3.451563 mhz. the default value of rtcon for an input frequency 3.58 mhz is a5h and for an input frequency of 3.456 mhz is 82h. table 11 comparator contents q27 q18 q11 comp_3.580 1 1 0 0 1 1 0 0 1 x x x x x x x x comp_3.456 1 1 0 0 0 1 0 1 1 x x x x x x x x bit 7 ? rtcon ? bit 0 handbook, full pagewidth mgm770 17 17 17 q11 to q27 emg_clk q10 q0 28 bit ripple comp_3.456 comp_3.580 0 1 rtc_mode 0: rtc_clk = 3.456 mhz 1: rtc_clk = 3.580 mhz synch_reset rtc_event fig.6 real-time clock (rtc) generation.
2001 apr 17 20 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 10 the microcontroller the embedded ms80c51 microcontroller controls the digital telephone answering machine (dtam) chip by means of special function registers (sfrs). sfrs are defined for the blocks mcb, ticb, pcon, dsp, i 2 c-bus, ports p1, p3 and p4, ma, msk and ana (the analog blocks). all of these (except sfr pcon) are shown in the block diagram in fig.1. the architecture of the microcontroller itself and the interface to these blocks are described in this chapter. 10.1 microcontroller architecture the microcontroller architecture and its environment is shown in fig.7. the microcontroller has some application-specific peripherals such as the i 2 c-bus, watchdog timer (wd), p1, p3, p4, mcb, external interface with ma port, sfrs of the dsp block, the ticb and the ana block. most of these functions and sfrs are located in the application specific function block (asf), see fig.7. the 80c51 core contains the 80c51 standard functions such as timer 0 and timer 1, power-down/idle states and a 15 vector dual-level interrupt controller int15l2. furthermore, the microcontroller contains the metalink enhanced hooks protocol which enables metalink emulation via ale, psen, ea, p0 and p2. the external program memory access is done via the standard ports p0 and p2. connection of external flash memory is done via the p4, p0 and p2 i/o pads. the microcontroller clock driver (cd) has no clock divider, which means that the microcontroller operates on 6 microcontroller_clk clocks per machine cycle. the 80c51 has a few basic modes of operation: reset, normal, metalink, test (various) idle and power-down. entering the metalink mode can be done via inputs ale and ea during a reset. the idle mode can be entered by setting the idl bit in the pcon register. leaving the idle mode can be done via a master reset (rstin), any external interrupt, a dsp_event, time_event or rtc_event, timer 0 and timer 1, i 2 c-bus interrupt, msk_event or fs_event; if these interrupts are enabled. the power-down mode can be entered by setting the pd bit in pcon. the power-down logic of the microcontroller will turn all microcontroller clocks off. the time_event, dsp_event, rtc_event and ex2 to ex6 are mixed with ex0 (see fig.10) and therefore make use of the standard wake-up circuitry of the 80c51. these interrupts should be active for more than 6 clocks (read, modify, write of irq1 takes 1 instruction) to guarantee the interrupt for the microcontroller. setting the pd bit of pcon after setting the system-off bit of spcon, will trigger the analog section to turn off the oscillator and therefore the whole chip. in order to keep static supply currents minimal, it is advised to switch off the digital-to-analog part of the codecs before going in this system-off mode. wake-up from system-off can be done via a rstin or an external interrupt ex0 to ex6 (if the ex0 interrupt is enabled) or ex1 (if the ex1 interrupt is enabled). a wake-up from system-off will always reset the pcd6003. the ex interrupt condition should last more than 4096 + 64 + 4 clocks to be sure that the interrupt is handled when entering the normal mode. if the interrupt is shorter the microcontroller will only enter the normal mode after the reset is gone. 10.2 memory mapping the memory map of the 80c51 is shown in fig.8. in addition to all the sfrs, the microcontroller has 128 bytes of directly addressable (data) memory, 128 bytes of indirectly addressable (idata) memory and 512 bytes of aux ram, the on-chip movx addressable (xdata) memory. on-chip xdata memory access can be disabled by setting the ard bit in pcon to logic 1. the internal 32-kbyte rom of microcontroller program (code) memory can be accessed when ea is set to logic 1. via ports p0, ma, p2 and p4 it is possible to access up to 512 kbytes of external speech data memory stored in a parallel flash memory. a cad flash memory can also be mapped in this area. a serial (spi or microwire compatible) flash memory can be connected to p4 which is controlled by the mcb. up to 64 kbytes of program (code) memory can be connected to the p0, p2 and psen pads. this can be any external program memory (like the mon51 target debug rom) if ea is logic 0. when the eam sfr bit (p4cfg.5) is logic 0 (default after reset), the xram-mapped control registers can only be accessed if p4.3 is logic 1. otherwise, xram addressing is independent of the value of the p4.3 sfr bit.
2001 apr 17 21 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 handbook, full pagewidth mgt432 irq1/ix1 group if msk ticb ana analog functions dsp i/o pads p1, p3 rd,wr flash i 2 c-bus flash cad flash parallel flash microwire/ spi external 64-kbyte sram i/o pads p4 dsp cd msel port1 wd wdrst port3 mode control ramif cpu xmemu port4 i pad rst_in i pad rst_ana o pad mrst o pad dis_xtal i 2 c-bus i 2 c-bus_int ard pcon.2 to pcon.7 mcb i/o pads p0, p2 psen ea ale sf group int. timer 0 timer 1 pcon.0 to pcon.1 int15l2 sram main/aux ram 256/512 bytes application specific functions ex0 to ex6 dsp_req msk_int romif internal 32 kbyte rom m cms 80c51 core m c_clk mrst osc_off pad_ale pad_ea_n ticbif spcon[7] dsp_event time_event rtc_event fs_event ticb dram aram fig.7 microcontroller (ms 80c51) architecture and environment.
2001 apr 17 22 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 handbook, full pagewidth mgt433 external program memory external data memory internal xdata memory internal rom aux ram confreg ma p2 ea = 1 xdata idata main ram sfr data 128 255 48 32 0 bit addressable space register banks 0 to 3 p4.3 = x ard = x p4.3 = 0 ard = 1 xdata ard = 0 p4.3 = x ard = 1 code code 64k 32k 518 515 512 ea = 1 xdata-mapped registers p4.3 = 1, eam = 0, ard = x or ard = 0, eam = 1, ea = 1 fig.8 microcontroller memory map.
2001 apr 17 23 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 10.3 sfr mapping the sfr mapping for the microcontroller is shown in table 12. all sfrs and their reset states are described in table 13. table 12 sfr mapping notes 1. sfrs in this column are both bit and byte-addressable. 2. complies to 80c51 family architecture specification. 3. these registers are read only (all other sfrs are read/write). 4. reserved register, used for testing purposes. writing of reserved or undocumented bits might lead to unexpected behaviour of the device (see section 10.8). sfr address (hex) special function registers 8 bits each addressable (1) only byte addressable f8 to ff ip1 (2) - - ---- wdt (2) f0 to f7 b (2) - - ---- wdtkey e8 to ef ien1 (2) ix1 - ----- e0 to e7 acc (2) - - ----- d8 to df s1con (2) s1sta (2)(3) s1dat (2) s1adr (2) ---- d0 to d7 psw (2) - - ----- c8 to cf mcon mbuf mstat ----- c0 to c7 irq1 intc gpadr (3) gpadc gpdar symod - dtcon b8 to bf ip0 (2) xwud v refr cdvc1 cdvc2 cdtr1 (4) - tctrl (4) b0 to b7 p3 (2) ---- pmtr1 (4) pmtr2 (4) cdtr2 (4) a8 to af ien0 (2) mcsc mcsd altp ---- a0 to a7 -- dtm0 (3) dtm1 (3) dtm2 (3) mtd0 mtd1 mtd2 98 to 9f p4 spcon ckcon rtcon - cdtr1 (4) - p4cfg 90 to 97 p1 (2) - - ----- 88 to 8f tcon (2) tmod (2) tl0 (2) tl1 (2) th0 (2) th1 (2) -- 80 to 87 - sp (2) dpl (2) dph (2) --- pcon
2001 apr 17 24 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 table 13 microcontroller register list name address (hex) description reset state (1) acc e0 accumulator 0000 0000 altp ab le and gpc control x 000 0000 a - accumulator 0000 0000 b f0 b register for multiply, divide or scratch 0000 0000 ckcon 9a clock control register 0000 0000 cdvc1 bb codec digital volume control for codec1 00 xx 0 xxx cdvc2 bc codec digital volume control for codec2 00 xx 0 xxx cdtr1 bd codec test register 1; see note 1 00 xx 0 xxx cdtr2 b7 codec test register 2; see note 2 00 xx 0 xxx dtcon c7 line selection and alternative gain control register xx 00 x 00 x dpl 82 data pointer low 0000 0000 dph 83 data pointer high 0000 0000 dtm0 a2 dsp to microcontroller communication register 0 (read only) 0000 0000 dtm1 a3 dsp to microcontroller communication register 1 (read only) 0000 0000 dtm2 a4 dsp to microcontroller communication register 2 (read only) 0000 0000 gpadc c3 automatic analog-to-digital conversion, channel select, request con?rm xxxx x 000 gpadr c2 digital value of analog input (read only) 0000 0000 gpdar c4 digital value of analog output 1000 0000 ien0 a8 interrupt enable register 0 0000 0000 ien1 e8 interrupt enable register 1 0000 0000 intc c1 interrupt control register xxxx xx 00 ip0 b8 interrupt priority register 0 x 000 0000 ip1 f8 interrupt priority register 1 0000 0000 irq1 c0 interrupt request flag register 0000 0000 ix1 e9 interrupt polarity register xxx 0 0000 mcsd aa memory control serial data register 0000 0000 mcsc a9 memory control serial command register xxxx 0000 mtd0 a5 microcontroller to dsp communication register 0 0000 0000 mtd1 a6 microcontroller to dsp communication register 1 0000 0000 mtd2 a7 microcontroller to dsp communication register 2 0000 0000 mcon c8 msk control register 0000 0000 mbuf c9 msk data buffer register xxxx xxxx mstat ca msk status register 0x00 0000 p1 90 general purpose digital i/o 1111 1111 p3 b0 general purpose digital i/o 1111 1111 p4 98 p4 can be used to control ?ash memory xx 01 1110 p4cfg 9f p4 con?guration and addressing mode register 0000 0000 pcon 87 power and interrupt control register x 000 0000 pmtr1 b5 power management test register 1; see note 2 0000 0000
2001 apr 17 25 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 notes 1. all sfr bits with reset state x are either spare (i.e. have a memory bit in this position with reset state 0) or - (i.e. do not have a physical memory bit in this position). all spare bits can be addressed and used as additional general purpose bits. all bits marked - cannot be addressed by the user. to see which bits are spare or - refer to the respective sfr layouts. 2. reserved registers, used for testing purposes. writing of undocumented or reserved bits might lead to unexpected behaviour of the device (see section 10.8). pmtr2 b6 power management test register 2; see note 2 0000 0000 psw d0 program status word 0000 0000 rtcon 9b real-time clock control 0000 0000 s1con d8 i 2 c-bus serial control register 0000 0000 s1adr db i 2 c-bus own slave address register 0000 0000 s1dat da i 2 c-bus data shift register 0000 0000 s1sta d9 i 2 c-bus status register (read only) 1111 1000 symod c5 analog system mode control 0000 0000 spcon 99 system power and clock con?guration 0 xx 0 0000 sp 81 stack pointer 0000 0111 tcon 88 timer/counter control register 0000 0000 tmod 89 timer/counter mode control register 0000 0000 tl0 90 timer low register 0 0000 0000 tl1 91 timer low register 1 0000 0000 th0 92 timer high register 0 0000 0000 th1 93 timer high register 1 0000 0000 vrefr ba voltage reference register 1010 0000 wdt ff watchdog timer 0000 0000 wdtkey f7 watchdog key register 0000 0000 xwud b9 external wake-up disable 0000 0000 name address (hex) description reset state (1)
2001 apr 17 26 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 10.4 microcontroller interrupts the microcontroller has 15 interrupt sources, shown below, which can be programmed to have a low or high priority. if enabled these interrupts sources result in jump to the addresses shown in table 14. ex2 to ex6 asynchronous external interrupts via p1.0 to p1.4 ex0 and ex1 asynchronous external interrupts via p3.2 (int0n) and p3.3 (int1n) dsp_event fs_event time_event i 2 c-bus interrupt rtc_event timer 0 and timer 1 interrupt msk interrupt. the external interrupt configuration of p1 is shown in fig.9. pins p1.5, p1.6 and p1.7 cannot be used as external interrupts. the ix1 sfr determines the polarity of the external interrupt sources of p1. clearing the global enable bit in ien0 disables all interrupt sources. using ien0 (and ien1) each individual external interrupt can be enabled or disabled. the irq1 sfr stores all external interrupts. so if an external interrupt with a low priority is detected during execution of another (high or low priority) interrupt it will be handled just after the return of this interrupt. the interrupt service routine for an external interrupt must clear the right irq1 flag to indicate that it has serviced the interrupt request. notice that during the interrupt routine this flag can be set again immediately after clearing the irq1 flag if the interrupt source is (still) high. the complete interrupt system is shown in fig.10. all 15 interrupts are allocated and can be given a low or high priority according to the setting of ip0 and ip1. each interrupt source can be individually enabled by means of ien0 and ien1. the irq1 and ix.7 registers are clocked (a clock which is active during idle) and can be set by p1.0 to p1.4, the time_event, the dsp_event, the fs_event and the rtc_event. these flags can only be cleared by software. only tcon.1, tcon.3, tcon.5 and tcon.7 flags are cleared by the interrupt controller hardware. all other flags must be cleared by software. the polling of a potential interrupt goes from a high priority to a low priority interrupt. within a high (or low) priority interrupt level the ex0 (if set to high priority) will be polled first followed by the next high priority interrupt. the interrupt sfrs ip0, ip1, ien0, ien1, irq1 and ix1 are defined in sections 10.4.1 to 10.4.6. a flag set to logic 1 in ip0 or ip1 (tables 15 and 16) causes the corresponding interrupt to have high priority.
2001 apr 17 27 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 table 14 allocation of interrupt sources notes 1. for some c-compilers 1 has to be added to this number. 2. the interrupt controller supports up to 15 interrupt sources, each with a 2-level (high or low) priority. high priority interrupt is always serviced before a low priority interrupt, but within the high and low levels, interrupts are serviced in the order shown in this column. vector source number (1) priority (2) description ienx/ipx 0003 ex0 0 1 external interrupt 0 ien0.0/ip0.0 000b t0 1 4 timer 0 interrupt ien0.1/ip0.1 0013 ex1 2 7 external interrupt 1 ien0.2/ip0.2 001b t1 3 10 timer 1 interrupt ien0.3/ip0.3 0023 msk_event 4 13 msk ri or ti interrupt ien0.4/ip0.4 002b time_event 5 2 time interrupt ien0.5/ip0.5 0033 fs_event 6 5 fs interrupt ien0.6/ip0.6 003b ex2 7 8 external interrupt 2 ien1.0/ip1.0 0043 ex3 8 11 external interrupt 3 ien1.1/ip1.1 004b ex4 9 14 external interrupt 4 ien1.2/ip1.2 0053 ex5 10 3 external interrupt 5 ien1.3/ip1.3 005b ex6 11 6 external interrupt 6 ien1.4/ip1.4 0063 i 2 c-bus 12 9 i 2 c-bus interrupt ien1.5/ip1.5 006b dsp_event 13 12 dsp interrupt ien1.6/ip1.6 0073 rtc_event 14 15 rtc interrupt ien1.7/ip1.7 handbook, full pagewidth mgm773 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 ix1 ien1 rtc fs time ex6 ex5 ex4 ex3 ex2 irq1 rtc_event dsp_event time_event fig.9 port 1 external interrupt configuration.
2001 apr 17 28 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 10.4.1 i nterrupt p riority r egister 0 (ip0) table 15 interrupt priority register 0 (sfr address b8h); reset state 00h 10.4.2 interrupt priority register 1 (ip1) table 16 interrupt priority register 1 (sfr address f8h); reset state 00h 76 543210 - priority fs_event priority time priority msk priority t1 priority ex1 priority t0 priority ex0 76543210 priority rtc priority dsp priority i 2 c priority ex6 priority ex5 priority ex4 priority ex3 priority ex2 handbook, full pagewidth mgm774 time_event fs_event dsp_event rtc_event ex6 ex5 ex4 ex3 ex2 ix.4 ix.3 ix.2 ix.1 ix.0 msk t1 ex1 t0 ex0 i 2 c-bus tcon.0 tcon.1 ien0.0 ien0.1 ien0.2 ien0.3 ien0.4 ien0.5 ien0.6 ien1.0 ien1.1 ien1.2 ien1.3 ien1.4 ien1.5 ien1.6 ien1.7 tcon.5 tcon.3 tcon.7 mstat.0 mstat.1 s1con.3 intc.0 irq1.0 irq1.1 irq1.2 irq1.3 irq1.4 irq1.5 irq1.6 irq1.7 clocks exp1n xwud.0 to xwud.7 xwud edge/level source flags enable tcon.2 ip0.0 ip0.1 ip0.2 ip0.3 ip0.4 ip0.5 ip0.6 ip1.0 ip1.1 ip1.2 ip1.3 ip1.4 ip1.5 ip1.6 ip1.7 priority interrupt scanning interrupt controller exp1n + xwu polarity fig.10 pcd6003/80c51 interrupt system.
2001 apr 17 29 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 10.4.3 i nterrupt e nable r egister 0 (ien0) table 17 interrupt enable register 0 (sfr address a8h); reset state 00h 10.4.4 i nterrupt e nable r egister 1 (ien1) table 18 interrupt enable register 1 (sfr address e8h); reset state 00h 10.4.5 i nterrupt r equest f lag r egister (irq1) table 19 interrupt request flag register 1 (sfr address c0h); reset state 00h; note 1 note 1. the flags of irq1 will be set to logic 1 by hardware if the interrupt occurs. they must be cleared by software in the interrupt service routine. 10.4.6 i nterrupt p olarity r egister (ix1) table 20 interrupt polarity register (sfr address e9h); reset state 00h; note 1 note 1. a polarity bit set to logic 1 in ix1 will cause the external interrupt to be active high. 10.4.7 i nterrupt c ontrol r egister (intc) table 21 interrupt control register (sfr address c1h); reset state 00h 10.4.8 e xternal w ake - up d isable r egister (xwud) table 22 external wake-up disable register (sfr address b9h); reset state 00h 76543210 global enable enable fs_event enable time enable msk_event enable t1 enable ex1 enable t0 enable ex0 76543210 enable rtc enable dsp enable i 2 c enable ex6 enable ex5 enable ex4 enable ex3 enable ex2 76543210 rtc ?ag dsp ?ag time ?ag ex6 ?ag ex5 ?ag ex4 ?ag ex3 ?ag ex2 ?ag 76543210 spare spare spare polarity ex6 polarity ex5 polarity ex4 polarity ex3 polarity ex2 76543210 spare spare spare spare spare spare extended wake-up; xwu fs ?ag 76543210 rtc xwu disable dsp xwu disable time xwu disable ex6 xwu disable ex5 xwu disable ex4 xwu disable ex3 xwu disable ex2 xwu disable
2001 apr 17 30 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 10.5 interface to dsp the dsp to microcontroller interface (dmi) can be used for the following purposes: transferring compressed speech data from microcontroller to dsp transferring compressed speech data from dsp to microcontroller transferring dsp parameters (dsp mode, tone frequency etc.) from microcontroller (api) to the dsp transferring dsp events (caller id, ring detect, vox, call progress etc.) to the microcontroller. the microcontroller and the dsp can communicate by means of 6 sfrs (mtd0, mtd1 and mtd2 and dtm0, dtm1 and dtm2) and 4 dsp i/o registers (dtmc, dtmd, mtdc and mtdd), see fig.11. the dtmc and mtdc registers are used for communication and control and the dtmd and mtdd registers for transferring data. the micro transmit (mt), dr (dsp receive) and dt (dsp transmit), micro receive (mr) ensure that either the old data is read or new data is read although the dsp and microcontroller operate on different clocks. this can be achieved by means of simple handshake circuitry in either direction. the dr state machine ensures that the dsp will never read new mtdc control data and old mtdd speech data. in order to guarantee proper transitions of the dr state machine the dsp always has to read the dtmc first and afterwards the dtmd io register. the ticb generates the dsp_event interrupt when it receives a dsp_uc_req signal. the dsp_uc_req cannot be generated by the microcontroller because the dsp_event interrupt must be able to wake-up the microcontroller from power-down. mtd0/1/2 are written by the microcontroller. after each write to mtd0 the contents of mtd0/1/2 are transferred to the 16-bit register mtdd and the 8-bit register mtdc (the msb is set to 00h), which can be read by the dsp via the dsp i/o bus. in this way the dsp always receives a valid control byte and a valid 16-bit data word. if mtd0 is written while the dsp is turned off the mtd0 value will be transferred to the mtdc io-register as soon as the dsp is turned on. the mtdc and mtdd registers are continuously and immediately read by the dsp after every fs1 interrupt. the microcontroller can write a new word to mtd0/1/2 but has to wait for at least 125 m s to be sure that the dsp has read the previous value. dtm0/1/2 are read by the microcontroller as sfrs. the contents of the dtmd and dtmc registers are transferred to the dtm0/1/2 sfrs when the dsp writes the dtmc register. at this time an interrupt signal called dsp_event is generated to the microcontroller, which triggers the microcontroller to read the dtm0/1/2 sfrs. in this way dsp events and speech data can be transferred easily to the microcontroller. the dsp will transfer a maximum of 3 bytes, one command byte and two data bytes, for example; every 125 m s to the microcontroller. thus one write to dtmc takes place every 125 m s. similarly, the microcontroller can transfer a maximum of 3 bytes every 125 m s to the dsp. thus one write to mtd0 takes place every 125 m s. the default rate for the fs_event interrupt will be fs1/8 resulting in a data transfer rate of 10 words every 10 ms which equals 16 kbits/s. in case a higher rate is needed the fs_event interrupt rate can be switched to fs1/4. 10.6 interface to real-time clock (rtc) when the rtc_event interrupt is enabled in ien1 and the global enable bit in ien0 is set and the pcd6003 is not in emergency mode (ckcon.7 = 1), the microcontroller will get an rtc_event interrupt every 1 minute. the rtc interrupt service routine must clear the rtc flag. the rtc_event interrupt will also wake-up the microcontroller when it is in the power-down or in the idle state. under power saving conditions this will allow the user to switch off the microcontroller and still maintain an accurate real time clock.
2001 apr 17 31 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 handbook, full pagewidth mgm775 lsb dtmc lsb mtdc dr mtdc/d write rd_mtdd rd_mtdc mt dt dtmc write m c_dsp_ack dsp_ m c_req m c_dsp_req dsp_ m c_ack dsp_ m c_req dsp_clk m c_clk dsp_event dtm0, dtm1 or dtm2 fs1 interrupt fs_event mr lsb dtmd msb mtd0 write lsb mtdd msb dtm0 mtd0 dtm1 dtm2 mtd1 mtd2 rd16010 micro- controller 80c51 dsp io ticb m cms 80c51 sfr fig.11 dsp to microcontroller interface (dmi).
2001 apr 17 32 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 10.7 interface to the memory control block (mcb) the mcb is a 3-wire serial interface designed to interface with a versatile range of serial flash memories (both microwire and spi mode 0/3 compatible slave devices) in parallel with program otp/external rom and even external data sram. the 3-wire serial interface consists of a serial data output (fso) serial data input (fsi) and a serial clock signal (fsk). fsk, fso and fsi are alternative functions of the general purpose i/o pins p4.1, p4.2 and p4.4. the serial interface is controlled via the mcsc and mcsd sfrs. the fsk and fso outputs are both open-drain and must be pulled to 3 v with external resistors r fsk and r fso . the recommended value for both resistors at high fsk speeds (>1 mhz) is 1 k w . the mcsc sfr is defined in section 10.7.1. turning the mcb on by setting bit mcsc.3, will switch the fsk and fso pins to logic 0. a write to mcsd will generate the appropriate fsk/fso signal. a read from mcsd will only generate 8 fsk pulses and will shift-in the next byte. the shifting and the fsk/fso signal can be suppressed by setting bit 2 of mcsc. this can be used for reading the last byte out of the serial flash memory during a read sequence. the fsk shift off operation however is not necessary if the mcb is already turned off when reading the mcsd sfr for the last time. if a serial flash memory is chosen the fsk master clock rate can be selected with bits 0 and 1, as shown in table 24. the mcb is always master, which means that the fsk clock is always generated by the pcd6003. depending on the fsk clock rate, the shifting can continue for 8 32 microcontroller_clk periods. during this period, the microcontroller should not be put in a power saving mode (idle, power-down and system-off), otherwise the shifting will stop. data coming from or going to the serial flash memory can be accessed by means of the mcsd sfr. this is simply an 8-bit serial shift register. the first fso and fsi bits are always the most significant bits of mcsd. the first read of the mcsd sfr will only serially load the mcsd sfr with valid data. therefore, the first read operation must always be followed with another read operation which reads the actual received data out of the mcsd sfr. the serial shifting of bits into and out of mcsd is done at the same moment: 1 microcontroller clock before the falling edge of fsk (t sf ). when the fsk speed is programmed at the highest speed (microcontroller_clk/4) this shifting will be done in the middle of the fsk high level time. the most time-critical situation is when fsk is only 2 clocks wide and has a frequency of 3.5 mhz (14 mhz/4). in this case make sure that t r(fsk) , which can be controlled by the value of r fsk , is greater than the hold time requirement of the slave device. figure 12 shows how a microwire compatible device can be accessed with an fsk speed of microcontroller_clk/4. a spi mode 0/3 device requires an additional fsk clock falling edge to trigger the slave device to generate valid data on the fsi line. the spi mode 3 can be achieved by starting with fsk high when the device is turned on (turn mcb on after asserting the chip enable of the slave device) and by ending with fsk. the spi mode 0 can be achieved by generating an additional fsk pulse (by turning the mcb off and on again, see fig.12) between the last write to mcsd and the first read of mcsd. a variety of serial flash memory driver software packages is included in the api software for the microcontroller that is provided with the chip. an application note is available to help implementation of the software for the spi. 10.7.1 m emory c ontrol s erial c ommand r egister (mcsc) table 23 memory control serial command register (sfr address a9h) table 24 selection of fsk clock rate 76543210 spare spare spare spare mcb on shift off fsk rate 1 fsk rate 0 mcsc.1 mcsc.0 fsk clock rate 0 0 microcontroller_clk/4 0 1 microcontroller_clk/8 1 0 microcontroller_clk/16 1 1 microcontroller_clk/32
2001 apr 17 33 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 table 25 mcb timing notes 1. n depends on the chosen fsk clock rate and can be 4, 8, 16 and 32. 2. the rise time of fsk and fso depends on the externally connected pull-up resistor and the capacitive load. symbol parameter value t fsk fsk period n t micro_clock ; note 1 t su(fso) fso setup time with respect to the rising edge of fsk (n/2 + 1) t micro_clock - t r(fso) t h(fso) fso hold time with respect to the rising edge of fsk (n/2 - 1) t micro_clock - t r(fsk) t r(fsk) fsk rise time note 2 t r(fso) fso rise time note 2 t su(fsi) fsi setup time with respect to the internal shift clock (n/2 + 1) t micro_clock - t v(fsi) t h(fsi) fsi hold time with respect to the internal shift clock >t micro_clock t v(fsi) fsi valid time with respect to the falling edge of fsk depending on the used ?ash memory handbook, full pagewidth fso fsi fsk fso o2 o1 o0 o5 o4 data out data in o3 o6 o7 fsi fsk i7 i6 t h(fso) t r(fso) mgm776 mcb on mcsd write mcsd read slave shift in slave shift out slave shift out mcb shift off mcsd read mcb off t r(fsk) t v(fsi) t h(fsi) t fsk t su(fso) t su(fsi) fig.12 mcb timing for a microwire compatible device.
2001 apr 17 34 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 10.7.2 p arallel flash interface if a parallel (4-mbit) flash memory is chosen table 26 is valid. table 26 using p4 with 4-mbit parallel ?ash memory since parallel flash memory has a much larger addressing range than the 64 kbytes addressing capability of the 80cl51, additional addressing is done by means of the p4 sfr and the p4 i/o pad. the p4 sfr is connected to port p4 as shown in table 27. one pin is necessary to enable and disable the flash memory to reduce power consumption. four pins of p4 are necessary to connect various types of flash memories: a parallel flash: p4.0 to p4.2, p4.3, rd and wr are connected to ma[16:18], cen, oen and wn a serial flash: fso, fsi, fsc and p4.3 are connected to di, do, sk and cen pins a cad flash: p4.1 to p4.3, rd, wr are connected to cle, ale, cen, ren and wen pins. rd and wr are available as separate pins. if an access is done to the aux ram (ard bit of pcon equals logic 0) the rd and wr will be logic 1 on these pins. bits 1, 2 and 4 of port 4 are set to fsi, fsk and fso when a serial flash is selected in the mcsc sfr. the p4 sfr is defined in table 28. bits p4.6 and p4.7 are not available as addressable bits or port pins. p4 pin behaviour and configuration is described in more detail in section 16.2. p4.2 p4.1 p4.0 address 0 0 0 bank 0: 00000h to 0ffffh 0 0 1 bank 1: 10000h to 1ffffh 0 1 0 bank 2: 20000h to 2ffffh 0 1 1 bank 3: 30000h to 3ffffh 1 0 0 bank 4: 40000h to 4ffffh 1 0 1 bank 5: 50000h to 5ffffh 1 1 0 bank 6: 60000h to 6ffffh 1 1 1 bank 7: 70000h to 7ffffh table 27 p4 pin behaviour (alternative pin functions) note 1. the alternative outputs (gpc, fsi, fso, fsk and le) are connected with the general purpose outputs via an and logic gate. therefore when using the alternative functions the corresponding port bits have to be set to a logic 1. 10.7.2.1 port 4 register (p4) table 28 port 4 register (sfr address 98h); reset state 1eh 765 (1) 43210 -- p4.5/gpc p4.4/fsi p4.3 p4.2/fso p4.1/fsk p4.0/le 76543210 p4.7 p4.6 p4.5 p4.4 p4.3 p4.2 p4.1 p4.0
2001 apr 17 35 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 10.8 the test registers cdtrx, pmtrx and tctrl the special function registers cdtr1, cdtr2, pmtr1, pmtr2 and tctrl can put the dsp or codecs into various test modes. in these test modes normal operation is not guaranteed. the output behaviour of p3 can be changed and the dsp test modes can lead to a higher current consumption and to malfunction of the dsp. three bits however are accessible by the user: cdtr2.0, pmtr2.0 and pmtr2.2. see tables 29 and 30 for detailed description. table 29 cdtr2 (98h) bit assignment; reset state 00h table 30 pmtr2 (98h) bit assignment; reset state 00h notes 1. for minimum current consumption in pots mode (telephone line supplied operation), two bits of these registers have to be set (pmtr2.0 = 1, cdtr2.0 = 1). 2. for best noise performance of the sigma delta ad, chopping has to be enabled (pmtr2.2 = 1). 10.9 interface to timing and control block (ticb) the interface to the ticb consists of the special function registers spcon, ckcon and rtcon and the signals microcontroller_clk_en, microcontroller_clk, fs_event, time_event and rtc_event. the signals are described in section 10.1. 10.10 power and interrupt control register (pcon) table 31 power and interrupt control register (sfr address 87h); reset state 00h table 32 description of pcon bits 76543 2 10 reserved reserved reserved reserved reserved reserved reserved avo_off (1) 76543 2 10 reserved reserved reserved reserved reserved atc_chop_en (2) reserved avb_off (1) 76543 2 10 spare ard spare wle/ew gf1 gf0 pd idl bit symbol description 7 - spare, may be used as general purpose bit. 6 ard aux-ram disable. if ard = 1, then the access of a movx instruction to the 512 bytes of the aux-ram is disabled. if ard = 1, then a movx operation can access the lower 512 bytes of the external memory. the upper part of the external memory can always be accessed independently of the setting of the ard bit. 5 - spare, may be used as general purpose bit. 4 wle/ew watchdog load enable. this ?ag must be set by software prior to loading the watchdog timer. the ?ag is reset when the timer is loaded. see section 10.10.3 3 gf1 general purpose flag 1. 2 gf0 general purpose flag 0. 1pd power-down mode select. setting this bit activates the power-down mode; see section 10.10.2. 0 idl idle mode select. setting this bit activates the idle mode; see section 10.10.2.
2001 apr 17 36 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 10.10.1 i dle mode in the idle state timer 0 and timer 1 and the i 2 c-bus controller are still clocked. the cpu status along with all sfrs, main ram and aux ram registers are preserved. leaving the idle state can be done by any enabled interrupt or reset. the microcontroller hardware will clear the idle flag and start executing the interrupt. when the interrupt is serviced (reti instruction) the microcontroller will execute the next instruction following the instruction that put the microcontroller in the idle state. 10.10.2 p ower - down mode in the power-down state the clock of the entire microcontroller with its peripherals is off. the cpu status along with all sfrs, main ram and aux ram registers are preserved. leaving the power-down state can be done by any active enabled interrupt source or reset. the microcontroller hardware will clear the pd flag and start executing the interrupt. when the interrupt is serviced (reti instruction) the microcontroller will execute the instruction following the instruction that put the microcontroller in the pd state. toggling of the ale signal (for enhanced emc performance) is not supported. 10.10.3 t he w atchdog circuitry the purpose of the watchdog is to reset the microcontroller if it enters erroneous states caused by emi or bugs in the software that cannot be detected or eliminated. when enabled the watchdog circuitry will generate a reset if the user program fails to reload the watchdog timer within a specified length of time known as the watchdog interval. the watchdog interval is calculated as follows: the programmer should implement the following protocol: 1. write the key value 55h to the wdtkey sfr to disable the watchdog. 2. set the wle/ew bit to logic 1 to initially enable the watchdog. wle/ew now functions as a wle bit. only a reset can clear the ew bit. 3. enable the watchdog timer by writing a value not equal to 55h to the wdtkey sfr. this is only necessary if the previous value of the wdtkey register was 55h. the value after reset is 00h. 4. enable the load of the wdt sfr by setting the wle bit to logic 1. 5. load the watchdog interval by writing the required value into the wdt sfr. after the load the wle bit is set to logic 0 again by the watchdog hardware. the value of wdt is 00h after reset. 6. write a value not equal to 55h to the wdtkey sfr to enable the watchdog. 7. repeat steps 4 and 5 in the user software before the watchdog timer expires. note in metalink emulation mode the watchdog cannot be used, the watchdog reset will reset the entire chip. t wd 256 wdt C () 12 287 microcontroller_clk ------------------------------------------------------ =
2001 apr 17 37 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 10.11 i 2 c-bus the serial port i 2 c-bus is a simple bidirectional 2-wire bus for efficient inter ic data exchange. the i 2 c-bus consists of a data line (sda) and a clock line (scl). these lines also function as i/o port p1.7 and p1.6 respectively. the system is unique because data transport, clock generation, address recognition and bus arbitration are all controlled by hardware. the i 2 c-bus serial i/o has complete autonomy in byte handling and supports all four i 2 c-bus operating modes: master transmitter master receiver slave transmitter slave receiver. the i 2 c-bus block contains 4 sfr registers. the mode of operation is controlled by the s1con register. s1sta is the status register whose contents may also be used as a vector to various service routines. s1dat is the data shift register and s1adr is the slave address register. slave address recognition is performed by hardware. an application note is available to help implementation of the software for the i 2 c-bus. handbook, full pagewidth mgm777 s1adr data shift register s1dat sda bus arbitration logic scl bus clock generator microcontroller asf group interface s1con serial control register status register own address register s1sta fig.13 i 2 c-bus serial i/o.
2001 apr 17 38 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 10.11.1 s erial c ontrol r egister (s1con) two bits are affected by the i 2 c-bus hardware, the si bit is set to logic 1 when a serial interrupt is requested, and the sto bit is set to logic 0 (cleared) when a stop condition is present on the i 2 c-bus. the sto bit is also cleared when ens1 = 0. when the i 2 c-bus block is in the master mode the serial clock frequency is determined by the clock rate bits cr[2:0]. table 33 serial control register (sfr address d8h) table 34 description of s1con bits 76543210 cr2 ens1 sta sto si aa cr1 cr0 bit symbol description 7 cr2 clock rate. this bit along with bits cr1 and cr0 determines the serial clock frequency when i 2 c-bus is in master mode, see table 35. 6 ens1 when this bit is set to logic 0 the i 2 c-bus is disabled, outputs sda and scl are in the high-impedance state, and p1.6 and p1.7 function as open-drain ports. with this bit set to logic 1 the i 2 c-bus is enabled. the p1.6 and p1.7 port latch must be set to logic 1. 5sta start ?ag. when the sta bit is set to logic 1 in slave mode, the i 2 c-bus hardware checks the status of the i 2 c-bus and generates a start condition if the bus is free. if sta is set to logic 1 while the i 2 c-bus is in master mode, the i 2 c-bus transmits a repeated start condition. 4sto stop ?ag. with this bit set to logic 1 while in master mode a stop condition is generated. when a stop condition is detected on the bus, the i 2 c-bus hardware clears the sto ?ag. in the slave mode, the sto ?ag may also be set to logic 1 to recover from an error condition. in this case no stop condition is transmitted to the i 2 c-bus. however, the i 2 c-bus hardware behaves as if a stop condition has been received and releases sda and scl. the i 2 c-bus then switches to the not addressed receiver mode. the sto ?ag is automatically cleared by hardware. 3si i 2 c-bus interrupt ?ag. when this ?ag is set to logic 1, an acknowledge is returned (i.e. an interrupt is generated) after any one of the following conditions: a start condition is generated in master mode own slave address received during aa = 1 general call address received while s1adr[0] = 1and aa = 1 data byte received or transmitted in master mode (even if arbitration is lost) data byte received or transmitted as selected slave stop or start condition received as selected slave receiver or transmitter. 2aa assert acknowledge. when set to logic 1 an acknowledge will be returned during the acknowledge clock pulse on scl when: own slave address is received general call address is received while s1adr[0] = 1 data byte is received while device is a selected slave. with aa = 0 no acknowledge will be returned. consequently, no interrupt is requested when the own slave address or general call address is received. 1 cr1 clock rate. these 2 bits along with the cr2 bit determine the serial clock frequency when i 2 c-bus is in master mode, see table 35. 0 cr0
2001 apr 17 39 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 table 35 i 2 c-bus bit frequencies in master mode note that any i 2 c-bus device tolerates a maximum and sometimes a minimum scl frequency. the correct setting of bits cr2, cr1 and cr0 using a specific microcontroller clock frequency is therefore important. 10.11.2 s tatus r egister (s1sta) s1sta is an 8-bit read-only register. its contents may be used as a vector to a service routine. this optimizes the response time of the software and consequently the i 2 c-bus. table 36 status register (sfr address d9h); reset state f8h 10.11.3 d ata s hift r egister (s1dat) s1dat contains the serial data to be transmitted or data that has just been received. bit 7 is transmitted or received first. table 37 data shift register (sfr address dah); reset state 00h 10.11.4 a ddress r egister (s1adr) this 8-bit own address register may be loaded with the 7-bit address to which the controller will respond when programmed as a slave receiver/transmitter. the lsb bit gc is used to determine whether the general call address is recognized. table 38 address register (sfr address dbh); reset state 00h cr2 cr1 cr0 f microcontroller_clk divided by i 2 c-bus bit frequency (khz) at f microcontroller_clk 0.9 mhz 3.58 mhz 7.16 mhz 14.32 mhz 21 mhz 0 0 0 10 90 358 --- 0 0 1 20 45 179 358 -- 0 1 0 30 30 119 239 -- 0 1 1 40 22 90 179 358 - 1 0 0 80 11 45 89.5 179 269 1 0 1 120 7.5 30 59.7 119 179 1 1 0 160 5.6 22 44.8 89.5 134 111 - ----- bit symbol description 7 to 3 sc[4:0] contains the status code de?ned by the i 2 c protocol 2to0 - not used, all bits are 0 bit symbol description 7 to 0 s1dat[7:0] i 2 c-bus serial data bit symbol description 7 to 1 sla[6:0] own i 2 c-bus address 0 gc 0: general call address is not recognized 1: general call address is recognized
2001 apr 17 40 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 10.12 msk modem the msk modem is used for in-band signalling between handset and base in analog cordless telephone systems ct0, ct1 and ct1+. the msk modems receiver and transmitter can be enabled separately. receive and transmit interrupts can wake-up the microcontroller during its power saving idle mode. the baud rates are programmable between 1200 and 4800 baud. figure 14 shows the functional diagram of the msk modem. the min input is the alternative input of p3.7 and mout[2:0] is the alternative output of p3.0, p3.1 and p3.6. the rx and tx mute can be done in software by any pin of ma, p1, p3 and p2. the mti and mri interrupts are or-ed together to a single interrupt called msk_int. so the msk_in interrupt handler should investigate the status of the mri and mti bit in the mcon sfr. the mout[2:0] outputs and the min input are alternative functions of p3.0, p3.1, p3.6 and p3.7. the mout[2 :0] outputs are 111 when the msk transmitter is disabled (default after reset). therefore, p3.0, p3.1, p3.6 and p3.7 can still be used as general purpose i/o ports. setting bit 7 of mstat will invert the min polarity. the modem has the following features: full-duplex operation via 8-bit parallel interface; the message is fully manchester coded/decoded automatic detection of 16 bit manchester preamble pattern the last received 4 bits of the preamble pattern are programmable receiver full, transmitter empty indication bits manchester coding and decoding for clock recovery and early error detection programmable input polarity baud rate selection from 1200, 2400, 3600 and 4800 baud with internal modem timer receiver and transmitter off-states with no power consumption.
2001 apr 17 41 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 handbook, full pagewidth mgt434 mpol receiver transmitter mout0 mout1 mout2 r2 r1 r0 rf rf slicer min vout mstat mpr mclk mri ibd7 to ibd0 an7 to an0 msk_int mti mb0 mb1 mren mten mbuf mcon timer msk modem 80c51 core earpiece mouthpiece rx_mute tx_mute fig.14 msk modem functional diagram.
2001 apr 17 42 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 10.12.1 80c51 microcontroller interface . the modem block interfaces to the microcontroller via the interrupt signal msk_int and via the control and data sfrs mcon, mstat and mbuf. the msk modem receive and transmit registers are both accessed via the sfr mbuf. writing to mbuf loads the transmit register and reading mbuf accesses a physically separate receive register. 10.12.1.1 msk modem control register (mcon) table 39 msk modem control register (sfr address c8h) table 40 description of mcon bits note 1. if both the transmitter and the receiver are disabled (mten = 0 and mren = 0), the clock of the msk modem is switched off. it is advised to use this state for power saving. table 41 selection of the modems baud rates 10.12.1.2 msk modem status register (mstat) table 42 msk modem status register (sfr address cah), reset state 00h 76543210 mpr3 mpr2 mpr1 mpr0 mb1 mb0 mten mren bit symbol description 7 to 4 mpr[3:0] preamble pattern. these 4 bits de?ne the modems preamble pattern. 3 to 2 mb[1:0] rx/tx frequency. these 2 bits de?ne the modem transmit/receive frequency; see table 41. 1 mten modem transmitter enable. if set the transmitter is active and mout[2:0] will get the value <100> if no data is transmitted. if reset, mout[2:0] will get the value <111> to zero the currents in the resistive dac; see note 1. 0 mren modem receiver enable. if set the modem receiver is active and scans for manchester data; see note 1. mb1 mb0 modem baud rate 0 0 1200 baud 0 1 2400 baud 1 0 3600 baud 1 1 4800 baud 76543210 mpol - mrf mre mrp mrl mti mri
2001 apr 17 43 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 table 43 description of mstat bits 10.12.1.3 msk modem data buffer (mbuf) table 44 msk modem data buffer (sfr address c9h) table 45 description of mbuf bits bit symbol description 7 mpol min polarity switch. if mpol = 1, the value of the min pin is inverted before being applied to the msk block. 5 mrf modem receiver full ?ag. this bit is set when mbuf holds a newly received byte. mrf is reset if the receiver is disabled (mren = 0) or by reading mbuf. this bit is read-only. writing to it will have no effect. 4 mre modem receiver error ?ag. indicates the reception of a non-manchester bit. this bit is set by hardware and is reset by reading mbuf, by disabling the receiver (mren = 0) or by resetting mri. this bit is read-only. writing to it will have no effect. 3 mrp modem receiver preamble ?ag. this bit is set by hardware when the modem recognized the programmed preamble pattern (aaah, mpr3 to mpr0) after locking the receiver clock (mrl = 1). mrp is reset by hardware if the receiver is disabled (mren = 0) or if non-manchester data is received (mre = 1). this bit is read-only. writing to it will have no effect. 2 mrl modem receiver clock locked ?ag. this bit is set when the clock of the receiver is locked, i.e. when the receiver has detected manchester data but has not found the preamble pattern yet. mrl is reset when the receiver detects a non-manchester bit or when the receiver is disabled. this bit is read-only. writing to it will have no effect. 1 mti modem transmit interrupt ?ag. indicates mbuf is empty to accept a new byte for transmission. this bit is reset by writing to mbuf or by writing a 0 to it. writing a 1 to mti will set the bit. this allows to generate a hardware interrupt by software. 0 mri modem receive interrupt ?ag. indicates: modem receiver full (mrf = 1) or modem receiver error (mre = 1) or modem receiver preamble (mrp = 1) or modem receiver clock locked (mrl = 1) this bit is reset by reading mbuf or by writing a logic 0 to mri. a reset of mri will also reset mre. writing a logic 1 to mri will have no effect. 76543210 d7 d6 d5 d4 d3 d2 d1 d0 bit symbol description 7 to 0 d7 to d0 writing to mbuf will load the data in the transmit buffer and automatically start a transmission at mout if the transmitter is enabled (mten = 1). a new byte can be loaded after mti is set. if a new byte is loaded before the setting of mti then the previous byte will be lost. after data has been received at min, indicated by mri, the received byte can be read from mbuf.
2001 apr 17 44 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 10.12.2 d ata transmission data transmission is enabled if bit mten in register mcon is set to logic 1. if mten is logic 0 data transmission is disabled and mout[2:0] is set to <111> to zero the currents in the resistive dac. setting mten to logic 1 sets mout[2:0] to the idle value <100>. this results in a value close to 0.5v dd on the output signal of the external dac. transmission is started by loading the first byte into register mbuf. all bytes are transmitted starting with the msb. a message is transferred in a block of 3 or more bytes, the first two bytes being the programmed manchester preamble pattern. in order to insert the preamble pattern, the first two bytes aah and axh (with x being the mpr[3:0] values programmed in the receiver msk modem) have to be written to mbuf by software. after this, the first byte of the message is written to mbuf. as soon as mbuf is ready to accept new input, signal mti is set. a new byte written to mbuf automatically clears mti. the time between two mti interrupts is: (e.g. for 1200 baud, t = 6.7 ms). if no new byte is written to mbuf at the end of a byte transmission, the modem transmitter stops transmission and mout[2:0] is set to the idle state <100>. in this case mti must be cleared explicitly. if mten is reset during transmission, the transmitter will finish the transmission of the current byte and then will set mout[2:0] to the off state <111>. no interrupt on mti will be generated at the end of the transmission. during reception, a digital pll re-synchronizes on the active transition of every bit. this allows a continuous transmission of long messages. figure 15 shows a possible timing diagram of data transmission. t8 1 baud rate ------------------------ = handbook, full pagewidth mgm779 data adh data aah data aah data 55h data 55h write mbuf 55h write mbuf 55h 80c51 access mout mti tx_mute set mten clear mti write mbuf aah write mbuf aah write mbuf adh fig.15 data transmission timing diagram.
2001 apr 17 45 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 10.12.3 d ata reception a message is received as a block of one or more data bytes. when enabled, the receiver starts sampling min and tries to detect a manchester pattern. as soon as 3 consecutive manchester bits are detected the receiver clock is locked (mrl = 1) and the receiver starts scanning the incoming data for the programmed manchester preamble pattern. when the modem recognizes the preamble pattern, bit mrp is set to logic 1. if a non-manchester bit is detected before finding the preamble pattern then mrl is reset and mre is set to logic 1. the synchronization process has to restart. if the preamble pattern has been detected the receiver starts to manchester decode the incoming data bits and shifts them into an internal register. after eight bits the contents of the internal register are copied to mbuf and mrf bit is set to logic 1. the received byte can be read from mbuf while receiving continues in the internal register. if a non-manchester bit is received during data reception then mre is set to logic 1 and mrl and mrp are reset. the receiver has to resynchronize before receiving new data. whenever one of the bits mrf, mre, mrp and mrl is set the mri bit is also set and an mri interrupt is generated. this means that when an mri interrupt occurs the 4 status bits have to be polled by software. the bit mrl allows the software to decide very quickly whether an occupied channel contains manchester coded data or not. the mrp bit is used to find the start of data transmission in a message that is repeated over and over again. mre is used to detect a manchester error, which is a violation of the manchester coding rule that the received level should change in the middle of a bitcell. the mrf bit indicates that the data in mbuf is ready to be read by the software. during data reception the time between two settings of mrf (each one generating an mri interrupt) is; figure 16 shows an example of the timing diagram of data reception. t8 1 baud rate ------------------------ = handbook, full pagewidth mgm780 data 37 data aa data ad data 1f data 37 non-manchester (speech) non-manchester (speech) read mbuf 1f read mbuf 37 clear mri clear mri clear mri rx_mute should be generated by microcontroller upon interrupt rx_mute should be cleared by microcontroller at end of message write mren = 1 80c51 access min mri mrf mrl mrp mre fig.16 data reception timing diagram.
2001 apr 17 46 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 10.12.4 m anchester coding of data the bits of the data byte written in mbuf are manchester encoded as shown in fig.17. a logic 1 is coded as a low-to-high transition in the middle of a bitcell, a logic 0 is coded as a high-to-low transition.the manchester encoded signal contains redundancy for early error detection in received bits. a non-matching 1 and 0 or 0 and 1 pair indicates an error condition.the manchester encoded signal has a polarity change in each bitcell. 10.12.5 w aveform generation with mout[2:0] the 3 digital output pins mout[2:0] should be used as an input to a 3-bit external dac. the signals can be connected via external resistors r2, r1 and r0 to a summation point and then be filtered with an external capacitor c1. this 3-bit dac is shown in fig.17. table 46 gives the relationship between mout[2:0] and the voltage vout. table 46 vout as a function of mout[2:0]; note 1 note 1. resistor values are shown in fig.17. figure 18 shows the possible waveforms that are produced by the waveform generator. the horizontal axis shows the sample counter on which the waveform changes its value. each bit is built-up out of 2 40 samples (n 3.456 mhz crystal, ckcon.6 = 0) or 2 42 samples (3.58 mhz, ckcon.6 = 1). the vertical axis shows the values of mout[2:0], forming the inputs of the resistive dac. the first half of the waveform is determined by the previous and the current bit, whereas the second half of the waveform is determined by the current and the next bit to be transmitted. the count frequency of the sample counter depends on the programmed baud rate. if the transmitter is disabled with mten set to logic 0, mout[2:0] is <111> to save power in the resistive dac. if the transmitter is enabled and no data is transmitted, mout[2:0] has an idle value of <100>, which corresponds to 0.57v dd . handbook, halfpage mgm781 r0 waveform generator mout0 r1 mout1 vout r2 mout2 c1 10 nf fig.17 3-bit dac with mout[2:0]. r0 = r r1 = 0.48 r r2 = 0.25 r mout[2:0] vout 000 0 001 0.14v dd 010 0.29v dd 011 0.43v dd 100 0.57v dd 101 0.71v dd 110 0.86v dd 111 v dd
2001 apr 17 47 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 handbook, full pagewidth mgm787 111 101 011 001 010 3 6 10 30 34 37 40 46 53 61 80 000 100 110 001 53 61 111 101 011 001 010 3 6 10 30 34 37 40 46 80 000 100 110 110 111 101 011 001 010 3 6 10 30 34 37 40 43 46 50 70 74 77 80 000 100 110 111 111 101 011 001 010 19 27 34 40 43 46 50 70 74 77 80 000 100 110 100 111 101 011 001 010 19 27 34 40 46 53 61 80 000 100 110 101 111 101 011 001 010 3 6 10 30 34 37 40 43 46 50 70 74 77 80 000 100 110 000 111 101 011 001 010 19 27 34 40 46 53 61 80 000 100 110 010 43 111 101 011 001 010 19 27 34 40 46 50 70 74 77 80 000 100 110 011 fig.18 waveforms with mout[2:0] for previous, current and next bits to be transmitted.
2001 apr 17 48 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 10.12.6 s ynchronisation when enabled the receiver samples min with a frequency f=8 baud rate. the sampled values are shifted into an 8-bit shift register. this register is regularly checked whether it contains samples that fulfil the manchester coding rule i.e. whether there is a low-to-high or a high-to-low transition in the middle of the bitcell. the receiver searches for 3 consecutive sets of 8 samples that fulfil the manchester coding rule. if these sets have been found the clock is locked (mrl = 1) and the receiver starts looking for the manchester preamble pattern. from this point on the receiver uses a phase locked loop (pll) to adjust the synchronisation after each received manchester bit. 10.13 le control the le signal is the alternative output of p4.0 and can be turned on with altp bit 1. the le signal can be used to connect to the e input of 68xxx microcontroller compatible peripherals such as an lcd controller. if these peripherals have a slow access time the le signal can be made high earlier by setting bit 0 of altp. bit 0 of altp will be cleared by hardware after the execution of a movx instruction. the altp register is described in more detail in section 16.2. figure 19 shows the le signal shapes for early read and/or write when the p4.0 alternative port function for le is selected. in fig.19, the dtam wr signal is only shown for timing reference. neither wr nor rd are physically connected to the display. the display rs and r/w pin can be connected to port 2 or ma pins (logic 0 after reset) and controlled by software. the early le timing hardware makes it possible to access lcd drivers (or other peripheral devices with the same interface) which require a large access time (>3 microcontroller_clk). the display le pin (p4.0) rising edge is determined by software, by setting bit 0 and 1 of the altp sfr. in order to latch the port 0 data at the correct moment, the falling edge is determined by internal dtam hardware. this generates for the lcd write operation an le falling edge at 0.5 of a microcontroller clock before the falling edge of wr, such that the lcd data hold time (t h ) requirement is always fulfilled. figure 20 shows the le signal shape for normal read and/or write when the p4.0 alternate port function for le is selected. again, the dtam wr signal is only shown for timing reference. both the rising and falling edges of the display le pin (p4.0) are determined by hardware if only bit 1 of the altp sfr is set. this generates for the lcd write operation an le falling edge at 0.5 of a microcontroller clock before the falling edge of wr, such that the lcd data hold time (t h ) requirement is always fulfilled. the normal le timing is actually the inverted value of either the rd or wr signal. this timing can be used for peripheral devices that have an access time of less than 3 microcontroller_clk.
2001 apr 17 49 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 handbook, full pagewidth mbl271 pcd6003 lcd max may le p00 to p07 rs r/w n.c. e db0 to db7 software controlled edge timing software controlled rising edge timing hardware controlled falling edge timing software controlled edge timing command data data read write > 400 ns 1/2 m c_clk 1 m c_clk (rd) wr fig.19 early le timing.
2001 apr 17 50 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 handbook, full pagewidth mbl272 pcd6003 lcd max may le p00 to p07 rs r/w n.c. e db0 to db7 software controlled edge timing hardware controlled rising edge timing hardware controlled falling edge timing software controlled edge timing command data data read write 1/2 m c_clk 1 m c_clk (rd) wr fig.20 normal le timing.
2001 apr 17 51 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 11 dsp i/o registers for the dtam application, the dsp is connected with several peripherals as shown in fig.21. basically, the dsp is connected to the analog interfaces codec1 and codec2. the dsp communicates with the peripherals via the dsp i/o registers. the data transfer is performed by the 16-bit xd data bus. the i/o registers of the different i/o units are 16 bits wide. the microcontroller controls the dsp and is the link between an external speech memory and the dsp. the ticb provides the fs1 clock, which interrupts the dsp every 125 m s. 11.1 interface to codec the codec data buffers are used to exchange speech data between the dsp and the codecs (see fig.21). the digital decimation filter ddf writes equidistant in time 16-bit linear pcm samples to the dsp i/o registers cdc_di0 to cdc_di3 (address 01h to 04h for codec1 and address 09h to 0ch for codec2) at a rate of 32 khz. the digital noise shaper (dns) reads equidistant in time 16-bit linear pcm samples from the dsp i/o registers cdc_do0 to cdc_do3 (address 05h to 08h for codec1 and address 0dh to 10h for codec2) at a rate of 32 khz. the input registers cdc_di0 to cdc_di3 and the output registers cdc_do0 to cdc_do3 are also called data input/output dio registers.
2001 apr 17 52 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 handbook, full pagewidth mgm785 00h dtmc 00h mtdc ioa4 to ioa0 d15 to d0 mtdd dtmd 80c51 iomdi iomdo iomc cdc1_di0 cdc1_di1 cdc1_di2 cdc1_di3 cdc1_do0 cdc1_do1 cdc1_do2 cdc1_do3 cdc2_di0 cdc2_di1 cdc2_di2 cdc2_di3 cdc2_do0 cdc2_do1 cdc2_do2 cdc2_do3 iosr i/o control block dns ddf dns ddf dsp_iack fseo fsc fsc dck do di dck ticb real 16010 dsp core iom or digital codec1 (line codec) analog section codec1 digital codec2 (handsfree codec) analog section codec2 iack iorq data memory ioc ioa iod fig.21 dsp i/o architecture.
2001 apr 17 53 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 12 external memory interface the external memory interface consists of the interface from the 80c51 microcontroller to external flash memory and software debugging circuitry such as a metalink emulator or target debugger. the external memory interface is shown in fig.22. handbook, full pagewidth mbl284 80c51 mcb and p4 ea ale p0_int p2_int ard ale rst p4.3 rd wr pse p4.1/fsk p4.2/fso p4.4/fsi p4.0/le p4.5/gpc wncad sck/cle di/ale do psen e_lcd p0 p0 p1 p3 ma p2 ma p2 io7 to io0 cenflash oencad flash and lcd otp pcd6003 external memory interface control xram mapped registers fig.22 external memory interface.
2001 apr 17 54 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 the internal rom fetching will be activated by making ea a logic 1. if ea is logic 0 external program memory can be connected and the internal rom will be disabled. the external memory interface block contains the ma and p2 generation logic and registers. the p2 and ma latches have special enable signals. appropriate bits (magp and p2gp) in the control register make p2 and ma available as general purpose output ports or as the 80c51 address bus. the last option is necessary for target debugging ( ea = 0), external rom ( ea = 0) or parallel flash memory (magp = 1 and p2gp = 1). in these cases external latches must be provided if the application needs the p2/ma as general purpose output ports as well. the magp and p2gp signals are bit 3 and 4 of the configuration register latch. ma will be a general purpose output port when magp is set to logic 0 by software (default after reset). if magp is set to logic 1 the ma port operates as the lower 8 bits of the program/data address bus. p2 will be a general purpose output port when p2gp is set to logic 0 by software (default after reset). if p2gp is set to logic 1 the p2 port operates as the higher 8 bits of the program/data address bus. the accessability of the p2gp and magp bits of the confreg register in the external interface block depends on the value of the eam (p4cfg.5) sfr bit: when eam is logic 0 (default after reset), the xram-mapped control registers can only be accessed if p4.3 is logic 1 (compatible mode to pcd6002 dtam device). otherwise (i.e. when eam is logic 0), xram addressing is independent of the value of the p4.3 sfr bit, but needs ard to be logic 0 (only available when fetching from internal memory, i.e. ea is logic 1). the latches are used for the configuration, ma and p2 registers and they are mapped at addresses 200h to 202h of the external data memory map. refer to table 48. register confreg (2-bit): this is the configuration register. in this register single bits are set to control the functionality of the external outputs. the content of this register is given in table 49. with the bits p2gp (p2 general purpose) and magp (ma general purpose) the output function of ma and p2 is determined. with bit p2gp = 0 (reset value) the output p2 is latched and can be used as a general purpose output for example to drive leds. data can be written to the register p2 with a movx command. with p2gp = 1 the internal bus p2_int[7:0] is directly transferred to the output p2[7:0]. this mode is for example applied when using parallel flash. output p2[7:0] delivers then the high address byte for the parallel flash. with magp = 0 (reset value magp = 0) the output ma[7:0] can be used as a general purpose output. otherwise, output ma[7:0] serves as latch (with ale as enable signal) for the low address byte provided by a internal bus. register ma (8-bit): if ea = 1 (internal rom used) and magp = 0 (default after reset) the ma pins will output the contents of the ma register (0201h) which contains 00h after reset. the state of the ma pins can be changed by writing a new value to the ma register. this must be done with a movx instruction while the p4.3 bit or the eam bit is logic 1. register p2 (8-bit): if ea = 1 (internal rom used) and p2gp = 0 (default after reset) the p2 pins will output the contents of the p2 register (0202h) which contains 00h after reset. the state of the p2 pins can be changed by writing a new value to the p2 register.this must be done with a movx instruction while the p4.3 bit or the eam bit is logic 1. table 47 overview of p0/ma/p2 settings; notes 1, 2, 3, 4 and 5 notes 1. xa/xd: address and data during a movx instruction; pa/pd: address and data during a code fetch; gp: general purpose port; low: low address byte; high: high address byte. ea magp p2gp function p0/ma/p2 0 x x p0 = xa_low/xd/pa_low/pd, ma = xa/pa_low and p2 = xa/pa_high 1 0 0 p0 =xd, ma =gp and p2 = gp 1 1 0 p0 = xd, ma = xa_low and p2 = gp 1 0 1 p0 = xd, ma = gp and p2 = xa_high 1 1 1 p0 = xd, ma = xa_low and p2 = xa_high
2001 apr 17 55 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 2. writing magp/p2gp is independent of the setting of the p4.3 sfr bit if p4cfg.5 (eam) is set to logic 1, otherwise (eam logic 0) p4.3 must be logic 1. 3. the wr/ rd pins are always active when doing a movx. they can be turned inactive for movx below 200h by setting the ard bit in pcon in case the eam bit is set to logic 1. 4. p0/p2 are standard 80c51 ports. an external latch is not needed since the demultiplexing of p0 is taken over by the ma port. 5. the ma/p2/confreg registers are part of the auxiliary ram address space and can be disabled by setting the ard bit in pcon in case the eam bit is set to logic 1. table 48 external memory control registers table 49 con?guration register (confreg); reset state 00h 12.1 supported ?ash memories table 50 shows the ports that are available in an application using various flash memories. for all types of flash memory shown in table 50 (except for the parallel flash memory) at least 34 general purpose i/o pins can be used for the application (display, line interface, keypad and leds; for example). p0 can also be used for the application to connect memory mapped peripherals such as an lcd controller or keypad. p0 pins have no output latch, so data written to this port will not remain here. there are many different types of flash memories manufactured, and the pcd6003 will work with many of them. table 51 explains the most important characteristics of a few of the commercially available flash memories which can be connected to the pcd6003 directly. table 50 ports available for the application note 1. p0 can be used as a data bus for other peripherals if not conflicting with the flash memory. external memory control registers address p2/p0 (p4.3 = 1, eam = 0 or ard = 0, eam = 1, ea=1) reset value access confreg 0200h 00h r and w ma 0201h 00h r and w p2 0202h 00h r and w 76543210 --- p2gp magp --- flash memory ports used by flash ports available for application i/o i o i/o i/o o cad p0 - p4.1, p4.2 and p4.3 p1, p3, p4.0, p4.4 and p4.5 p0 (1) ma and p2 spi/microwire - p4.4 p4.1, p4.2 and p4.3 p1, p3, p4.0 and p4.5 p0 ma and p2 i 2 c-bus p1.6 and p1.7 -- p1, p3 and p4 (except p4.3) p0 (1) ma, p2 and p4.3 parallel p0 - ma, p2, p4.0, p4.1, p4.2 and p4.3 p1, p3, p4.4 and p4.5 p0 (1) -
2001 apr 17 56 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 51 selection of supported ?ash devices notes 1. supported by philips pcd6003 api 3.x software (not all necessarily supported in parallel at runtime, consult actual philips a pi specification for details). 2. with the aid of the internal flash data memory buffers. table 52 memory access time requirement the delay parameters are defined by the delay (capacitive load) of the address bus, data bus, rd and psen pins, the power supply voltage and the internal delay in the digital memory interface section. as shown in table 52 there is a trade-off between power consumption and m emory speed requirement. flash memory type number made by interface type size (mbit) min. write size (bytes) min. read size (bytes) min. erase size (bytes) t acc (ns) supply (v) typical stand-by current ( m a) om48101 (1) philips spi 4 1 (2) 1 264 - 2.5 2 at45db041a (1) atmel spi 4 1 (2) 1 264 - 2.7 8 at45db081 (1) atmel spi 8 1 (2) 1 264 - 32 at45db161 (1) atmel spi 16 1 (2) 1 528 - 33 at45db321 atmel spi 32 1 (2) 1 528 - 33 km29w040 samsung mux cad 4 32 1 4k 100 3 10 tc58a040f toshiba microwire 4 32 32 4k - 550 nm29a040 national semiconductors microwire 4 32 32 4k - 55 am29lv004 amd parallel 8 4 1 1 64k 100 3 1 am29lv400 amd parallel 8/16 4 1 1 64k 100 3 1 mbm29lv004 fujitsu parallel 8 4 1 1 64k 100 3 5 m29v040 sgs thomson parallel 8 4 1 1 64k 120 3 25 case memory type cen connection oen operation t acc requirement 1 rom/otp v ss psen t acc < (5/2 t microcontroller_clk ) - delay 2 cad/pf v ss rd t acc <(5 t microcontroller_clk ) - delay 3 rom/otp ale psen t acc <(2 t microcontroller_clk ) - delay 4 cad/pf ale rd t acc < (9/2 t microcontroller_clk ) - delay 5 rom/otp psen v ss t acc < (3/2 t microcontroller_clk ) - delay 6 cad/pf rd and wr rd t acc <(3 t microcontroller_clk ) - delay
2001 apr 17 57 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 12.1.1 dtam external memory using a parallel flash a parallel flash memory can be connected to the pcd6003 chip as shown in fig.23. the magp and p2gp bits in the xram-mapped configuration register (confreg) must be set. clearing p4.3 will enable the flash memory. 12.1.2 dtam external memory interface using a 4- wire serial flash a 4-wire serial flash memory (like spi or microwire flash memory) can be connected to the pcd6003 chip as shown in fig.24. p4.3 must be level shifted when using a 5 v serial flash memory. p4.1 and p4.2 must be pulled to 3 v with a resistor. when using a 5 v flash memory the do output of the flash must be level-shifted to 3 v with 2 resistors (1 and 1.5 k w ). handbook, full pagewidth mbl273 1 k w p4.3 1 k w cen rd oen wr wn ry/byn p3.x p1.x p2, ma7 to ma0 and p4.0 to p4.2 v dd3v p0 io7 to io0 a18 to a0 a19 pcd6003 4/8 mbit flash fig.23 parallel flash memory connection. handbook, full pagewidth mbl274 1 k w p4.3 1 k w cen p4.4/fsi do p4.2/fso di sk p4.1/fsk v dd3v v dd3v /v dd5v pcd6003 serial flash fig.24 serial flash memory connection.
2001 apr 17 58 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 12.1.3 dtam external memory interface using an i 2 c- bus serial flash an i 2 c-bus flash memory can be connected to the pcd6003 chip as shown in fig.25. handbook, full pagewidth mbl275 1 k w p1.6/scl 1 k w scl p1.7/sda sda v dd3v v dd3v pcd6003 i 2 c-bus flash fig.25 i 2 c-bus serial flash memory connection. 12.1.4 dtam external memory using a cad flash a cad flash memory can be connected to the pcd6003 chip as shown in fig.26. p4.3 must be pulled up to 3 v with a resistor. p4.1, p4.2, rd and wr must also be pulled to 3 v with a resistor. handbook, full pagewidth mbl276 1 k w p4.3 1 k w cen p4.x cle p4.y ale rd ren wr wen p1.x ry/byn v dd3v p0 io7 to io0 pcd6003 mux cad flash fig.26 mixed cad flash memory connection.
2001 apr 17 59 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 12.1.5 dtam external memory using dram or aram a standard dram or aram memory can be connected to the pcd6003 chip as shown in fig.27. when wr/ rd are not programmed as push-pull outputs, a 1 k w pull-up resistor has to be connected to v dd3v . handbook, full pagewidth mbl277 we oe casn d [ 3:0 ] a [ 11:0 ] rasn wr rd p3.x p0 [ 3:0 ] ma [ 7:0 ] p2 [ 3:0 ] p3.y pcd6003 aram dram fig.27 dram/aram memory connection. 12.2 dtam external interface during target debugging if the dtam chip is used with the tscope-51 target debug tool the dtam chip needs executable sram where the monitor program mon51 can store the program code. this sram is accessible by means of the rd, wr and psen signals. since connection to parallel flash memory with xsram and rom is the worst case situation this case is shown in fig.28. since it is not a commercial system additional logic can be connected to the dtam chip to create executable sram. the target debug logic only consists of combinational logic: cenrom ? p2.7, p2.6 or p2.5 cenflash ? p4.3 cenxsram ? ( psen or not cenrom) and ( rd or not cenflash) oenxsram ? psen and rd wrxsram ? wr. the port restore logic is necessary to make the ma/p2/p0 ports available for the application. the mon51 program is assumed to be in the lowest 8 kbytes of the rom. if the flash memory should be accessed clear p4.3 to logic 0. now the mon51 program has no access to the xsram with rd so no breakpoints are allowed in the code area where p4.3 is logic 0. set p4.3 to logic 1 again after the flash memory access to enable mon51 again to access the xsram. target debugging requires i 2 c-bus and one general purpose input port. this means that at least 31 i/o ports are available for the application (not using parallel flash) during target debugging.
2001 apr 17 60 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 handbook, full pagewidth mbl278 p4.3 cen rd oen wr wn ry/byn p3.x p3.z p1.x p4.0 to p4.2 p1.6/scl p1.7/sda p0 p2 ea psen ma io7 to io0 a18 to a0 a19 dackn scl sda pcd6003 4/8-mbit flash keil tscope-51 pc cen p0_r ma_r p2_r tx rx gnd oen wn io7 to io0 a15 to a0 64-kbyte xsram cen oen io7 to io0 a15 to a0 mon51 rom target debug logic and otp port restore i 2 c-bus to rs232 converter fig.28 flash, xsram and mon51 rom memory connection.
2001 apr 17 61 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 13 the codecs 13.1 de?nitions in the description of the codecs, amplitude units in db are used. the following definitions apply: dbm: used for absolute analog signal power levels. 0 dbm equals 1 mw power dissipation in 600 w . a single sinewave signal with a power level of 0 dbm corresponds to an rms voltage value of 774.6 mv. dbmp: used for absolute analog signal power levels with psophometric weighting according to ccitt recommendation g.223 . this unit is used to express analog noise power levels. dbm0: used for relative digital signal power levels. 0 dbm0 is defined in ccitt recommendation g.711 (section 4, table 5) . it follows that the maximum digital signal power level is 3.14 dbm0 (a-law). thus 3.14 dbm0 is the rms value of a sinewave signal whose peaks just reach the full-scale of the digital code. for the (internal) bitstream signal (output of ars and dns) the positive full-scale value is a continuous stream of ones, whereas the negative full-scale value is a continuous stream of zeroes. for the (internal) digital 14 or 16-bit words, represented in 2s complement (msb first) the positive full-scale value is a zero followed by 13 or 15 ones, whereas the negative full-scale value is a one followed by 13 or 15 zeroes. dbm0p: used for relative digital signal power levels with psophometric weighting according to ccitt recommendation g.223 . db: is used for the signal level gain between any two nodes within the speech path. as different signal representations are used within the speech path, the gain value depends on the used signal definitions. dbp: is used for the signal level gain between any two nodes within the speech path with psophometric weighting according to ccitt recommendation g.223 . the uniform pcm reference point is the (virtual) signal node in the dsp at the input of the pcm encoder for the analog-to-digital speech path and the output of the pcm decoder for the digital-to-analog speech path. 13.2 codec architecture the pcd6003 is provided with two codecs that perform the analog-to-digital and digital-to-analog conversion of speech signals. in fig.29, the codecs are the interface between the external analog peripherals and the dsp. codec1 is used for the line interface and codec2 is used for the loudspeaker and the microphone. the dtcon register bit dtcon.4 selects the input to codec1 (lifmin1 or lifmin2). the main codec functions are (refer to fig.29): amp - pre-amplifier ars - analog receive sigma delta adc ddf - digital decimation filter dns - digital noise shaper atd - analog transmit dac. for codec1 the balanced line interface input is fed to the ars block that performs analog-to-digital conversion, the gain of the input can be set to the amplification steps: 7, 23 and 35 db (see section 17.5 for typical/maximum gain specifications). this programmable range is used by the microcontroller on command of the dsp to perform limit or automatic gain control. the analog data is converted by ars to a bit stream. the basic sampling frequency (f s ) is 8 khz. the ddf decimates the bit stream down to 16-bit linear pcm data. the df has a gain of 3.14 db (which has to be added to the programmable ars gain) to achieve a uniform reference point at the dsp input for linear pcm data. finally, the dsp will decimate this data to 16-bit linear pcm data at a rate of 8 khz. the reverse operation is performed in the transmit path. the dsp produces 16-bit linear pcm to the dns. the atd which is a dac converts the bit stream into an analog signal. the converter has a programmable amplification range of 18 db. this programmability is - 12, - 6, +0 and +6 db. codec2 is built-up in a similar manner as codec1, the only difference being the microphone amplifier before the adc. this will amplify the balanced analog (microphone) signal in the receive path with a fixed +15 db (see section 17.5 for exact gain specifications). for direct connectivity of an external microphone, a software on/off switchable supply voltage is available. several registers are available for the codecs control: dtcon: for selecting the input to codec1 (dtcon.4 = 0 means lifmin1 is selected, dtcon.4 = 1 means lifmin2 is selected) and for alternative gain settings (see section 13.2.2) cdvc1: the volume control register for codec1 cdvc2: the volume control register for codec2 cdtrx: test mode control registers for both codecs pmtrx: test mode control registers for both codecs.
2001 apr 17 62 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 13.2.1 v olume c ontrol r egisters (cdvc1 and cdvc2) the volume control registers are identical and both are reset to 00h. table 54 is relevant to both registers. table 53 volume control register 1 (sfr address bbh); volume control register 2 (sfr address bch) table 54 digital-to-analog gain values note 1. in these gain values the - 4 db digital gain (software dsp output port gain of - 2 db and dns path gain of - 2 db) is not included as in previous pcd600x data sheets. 13.2.2 d ata c ontrol r egister (dtcon) table 55 data control register (sfr address c7h), reset state 00h table 56 analog-to-digital gain values notes 1. the 3.14 db digital gain of ddf hardware block is not included here. the nominal values given in this table are rounded for naming convention. see section 17.5 for exact typical/maximum gain specifications. 2. system application should be such that the maximum line input signal level does not exceed the specified value to avoid distortion (see section 17.5 for maximum input level specifications). at a maximum line input level of - 37 dbm full-scale control the internal adc can still be achieved by a maximum gain setting of 35 db. 3. system application should be such that the maximum differential microphone input signal level does not exceed the specified value to avoid distortion (see section 17.5 for maximum input level specifications). at a maximum microphone input level of - 52 dbm full-scale control the internal adc can still be achieved by a maximum gain setting of 50 db. the high dynamic range of the adc allows for additional digital gain up to 30 db by the dsp. 4. if the hi_gain1/lo_gain2 bit is set to logic 1, the value of bit 3 of cdvc1/2 and amp_en is overruled and the gain will be +35 db for codec1 and +7 db for codec2. 76543210 d/a.1 d/a.0 spare spare a/d spare spare spare cdvc1[7:4]/cdvc2[7:4] digital-to-analog gain for codec1 and codec2 (1) 00xx - 12 db 01xx - 6db 10xx 0 db 11xx +6 db 76543210 spare spare hi_gain1 linesel spare amp_ena lo_gain2 spare codec1 analog-to-digital gain and channel selection codec2 analog-to-digital gain cdvc1[3:0]/cdvc2 [3:0] analog-to-digital gain (1) codec1 (line) (2) codec2 (mic) (3) hi_gain1 (line)/lo_gain2 (mic) amp_ena = 0 amp_ena = 1 0xxx 7 db 23 db 38 db hi_gain1/lo_gain2 = 0 (4) 1xxx 23 db 35 db 50 db xxxx 35 db 7 db hi_gain1/lo_gain2 = 1 (4)
2001 apr 17 63 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 the analog and digital parts of both codecs can be independently activated by the symod register; see section 9.2.2. bit 4 of symod is used to activate the microphone supply voltage, if the bit is logic 0 the supply is off. the balanced microphone input has a minimum differential input resistance of r micdm , and the balanced line interface input has a minimum differential input resistance of r lifindm . the output resistance of the balanced codec outputs is r lifout for codec1 and r spkr for codec2 at a differential output level of 1350 mv (rms). for exact measurement conditions and specified values see section 17.5. handbook, full pagewidth mgt442 dtcon.4 cdvc1 ars1 atd1 ddf1 dns1 dt1 dr1 lifmout line interface output line interface input loudspeaker output microphone input receive path lifpout lifmin1 lifmin2 lifpin cdvc2 ars2 amp atd2 ddf2 dns2 dt2 dr2 transmit path micp micm spkrp spkrm codec1 codec2 dsp fig.29 block diagram of codecs.
2001 apr 17 64 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 14 analog voltage reference (avr) 14.1 bandgap reference the analog voltage reference circuitry (avr) includes a bandgap circuit with a nominal output voltage of about 1.25 v. this voltage is used by the power-on reset block and by the analog voltage source to generate the reference voltage v ref . block avr is always on, even in system-off mode, and will consume only a few m a of current. the output of avr is directly connected to the power-on reset block and it determines the power-on reset threshold levels accuracy in first order. the connection from avr to the analog voltage source circuitry (avs, see section 14.2) is via an internal series resistor of about 500 k w (typical). the voltage after this resistor is connected to pin v bgp , which allows an external capacitor (100 nf) to be connected to filter out any noise from avr otherwise entering avs. with this configuration the noise at pin v bgp will be about - 115 dbmp. the pin also allows a direct measurement of the bandgap voltage, but no current must be drawn. in order to guarantee a correct start-up of the bandgap voltage under all conditions, a supply voltage ramp test is performed on each device. the bandgap voltage is compared against specified values at the indicated times (see fig.30). the test setup intends to reflect the worst case start-up conditions which may occur in an application (for initial power-up and after short power drop). note that t rise is critical and should not be greater than indicated in a given application. other indicated times (t settle and t rise ) reflect the worst case conditions for the device and therefore can change in the application. handbook, full pagewidth mgt445 t fall t settle t rise t measure v bgp v dda 0 v 0.6 v 2.5 v t fall = 2 ms t settle = 45 ms t rise = 20 ms fig.30 bandgap voltage test setup.
2001 apr 17 65 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 14.2 analog voltage source (avs) the analog voltage source generates the following voltages: a precise reference voltage v ref . the value in register vrefr determines the v ref . in the application this voltage should be tuned to 2000 mv, since it will determine the absolute accuracy of the auxiliary analog-to-digital and digital-to-analog conversion. v ref is the direct output of an opamp which can source an output current, and not sink. an external capacitor should be connected between v ref and v ssa for stability and noise performance. the reference voltage can also directly supply an external electret microphone via pin v mic . the switch between v ref and v mic is controlled via bit 4 in the symod special function register. an analog output voltage daout. this voltage can be set between approximately 8 mv (1 lsb = v ref /256) and v ref (= 2000 mv) by changing the contents of register gpdar. this large range is possible when no opamp is used. this causes a relatively high output resistance with a settling time of about 10 ms. the dynamic switching of daout causes the output resistance to be dependent of the actual load on daout. this effect can be cancelled if an external capacitor larger than 500 pf between daout and v ssa is applied. this will however result in a slower settling time of the output voltage, to about 30 m s. the internal analog common mode voltage v acm , used in the codec. the internal voltage v adc is used only when an analog-to-digital conversion is executed. as mentioned above, for highest analog performance the reference voltage v ref has to be adjusted in the application to 2000 mv. for this purpose the vrefr sfr has been defined. the reset state should ensure that the reference voltage is about 2000 mv on a typical device. exact adjustment has to be done under software control using the vrefr register, where increasing the v refr value will decrease the reference voltage. 14.2.1 v oltage r eference r egister (vrefr) table 57 voltage reference register (sfr address bah); reset state a0h 76543210 vref.7 vref.6 vref.5 vref.4 vref.3 vref.2 vref.1 vref.0
2001 apr 17 66 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 15 iom 15.1 features the iom block in the pcd6003 is a 4-wire serial interface performing following functions: digital interface with up to two 64 kbits/s channels at a bit rate of n 256 kbits/s (n = 1, 2, 3, 4 or 8), complying with the iom-2 specifications (iom-2 is a registered trademark of siemens ag) digital interface with 32 slots/frame and non-doubled data clock; compatible with the digital interface of some speech codec ics autonomous storing/fetching of data into/from the dsp i/o registers byte or word (16 bits) transfer. 15.2 pin description the following pins are used by the iom interface: di: serial data input with a bit rate of n 256 kbits/s (n=1,2,3,4or8) do: serial data output with a bit rate of n 256 kbits/s (n=1,2,3,4or8) fsc: 8 khz frame synchronization input/output dck: data clock input/output. twice the data transmission frequency on di and do, except in the non-doubled data clock mode (see section 15.3). these pins are alternative functions of p3. when activated, do is an open-drain pin, as many devices must be able to write on the same data line in a time-multiplexed mode. therefore do must be externally pulled-up. fsc and dck are inputs or push-pull outputs, depending on the iom being in slave or master mode. activation of the iom alternative functions of p3 and switching between slave or master mode is controlled by the sfr altp, bit 6 and 5 respectively (see section 16.2 for more details). 15.3 functional description the digital interface of the pcd6003 can work at several bit rates, summarized in table 61. a particular bit rate is selected by writing the 3-bit code given in the first column of the table into the iom control register bits iomc[15:13]. choosing the code 000 or 001 deactivates the iom interface and stops all the transactions on the iom bus. this is the default state after reset. the pcd6003 iom can be master or slave. after reset the iom is in slave mode. switching between slave or master mode is controlled by the sfr altp, bit 6 and bit 5 respectively (see section 16.2.5 for more details). in slave mode both fsc and dck are inputs. in master mode both fsc and dck are outputs. in master mode fsc and dck are generated by the ticb (see section 9.1). master mode should only be used in combination with the bit rate 768 kbits/s. slave mode should only be used when operating with a 3.456 mhz (or multiple) crystal. in general, proper iom functionality is only guaranteed at dsp operating frequencies of 28 and 42 mhz. fsc is an 8 khz framing signal for synchronizing data transmission on di and do. the rising edge of fsc gives the time reference for the first bit transmitted in the first slot of a speech frame. the number of slots per speech frame depends on the selected data rate. each slot contains 8 data bits. dck is a data clock. its frequency is twice the selected data rate in iom mode. in speech mode, the dck frequency is equal to the data rate (2048 khz for 2048 kbits/s). di is the serial data input. data coming on di in packets of 8 bits (a-law pcm encoded data) or 16 bits (linear pcm data) is stored temporarily in an iom data buffer, from where it is processed by the on-chip dsp. on the other hand, data written into the iom data buffers by the dsp is shifted out on pin do. there are two iom data buffers, allowing the use of two 8-bit channel. one channel is 64 kbits/s in case of a-law pcm encoded data and 128 kbits/s if linear pcm data is transferred, in which case two consecutive slots are used. the speech mode was implemented to support the codec interface of some speech compression ics. this mode is very similar to the iom 32 slots mode, the main difference being the non-doubled data clock. see section 15.6 for timing information. 15.4 iom data buffers table 58 and 59 show the two 16-bit dsp registers used as data buffers: iomdi for storing inbound data and iomdo for the outbound data. the high bytes store the data of buffer 1, the low bytes the data of buffer 0.
2001 apr 17 67 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 15.4.1 iom d ata i n r egister (iomdi) table 58 iom data in register; reset state 00h 15.4.2 iom d ata o ut r egister (iomdo) table 59 iom data out register; reset state 00h 15.5 iom control register (iomc) the bit rates, the selection of active slots on the iom interface and the logic connection between an iom slot and an iom data buffer are defined in the iom control register. the iom modes which can be selected are listed in table 61. writing to the iomc register is done via the application programming interface (api) software. please refer to the api specification for more details. table 60 iom control register; reset state 00h table 61 selection of iom modes note 1. the speech mode is similar to the iom slave 32 slots mode, but with a non-doubled data clock dck. 1514131211109876543210 iom inbound data buffer 1 iom inbound data buffer 0 1514131211109876543210 iom outbound data buffer 1 iom outbound data buffer 0 151413121110987 6 5 43210 iom mode select iom buffer 0; slot position spare buffer 0 active buffer 1 active iom buffer 1; slot position iomc[15:13] mode 000 or 001 inactive (default after reset) 010 iom slave mode, 256 kbits/s in 4 slots/speech-frame 011 iom slave mode, 512 kbits/s in 8 slots/speech-frame 100 iom master/slave mode, 768 kbits/s in 12 slots/speech-frame 101 iom slave mode, 1024 kbits/s in 16 slots/speech-frame 110 speech slave mode, 2048 kbits/s in 32 slots/speech-frame (1) 111 iom slave mode, 2048 kbits/s in 32 slots/speech-frame
2001 apr 17 68 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 15.6 timing the timing on the 4-wire interface is given in fig.31 and table 62 for the iom mode and in fig.32 and table 63 for the speech mode. handbook, full pagewidth mgm794 dck fsc di/do dck fsc do di bit 7 bit 6 bit 5 t r(dck) t f(dck) t d(f) t wh t d(df) t d(dc) t su(f) t h(d) t su(d) t w(fh) t wl t dck bit 7 bit 7 fig.31 4-wire interface timing in iom mode.
2001 apr 17 69 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 table 62 timing parameters in iom mode notes 1. corresponds to the highest dck frequency allowed (4.096 mhz) with a 10% margin. 2. condition c l = 150 pf. symbol parameter min. max. units t r(dck) data clock rise time - 60 ns t f(dck) data clock fall time - 60 ns t dck data clock period 220 (1) - ns t wh data clock high time pulse width 80 - ns t wl data clock low time pulse width 80 - ns t r(fsc) frame sync rise time - 60 ns t f(fsc) frame sync fall time - 60 ns t d(fsc) frame sync delay time - t wl 60 ns t su(fsc) frame sync set-up time 60 - ns t wfh frame sync high time pulse width 130 - ns t d(dc) output data to data clock delay time - 100 (2) ns t d(df) output data to frame sync delay time - 150 (2) ns t su(d) input data set-up time t wh - ns t h(d) input data hold time 50 - ns
2001 apr 17 70 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 table 63 timing parameters in speech mode notes 1. corresponds to the dck frequency (2.048 mhz) with a 10% margin. 2. condition c l = 150 pf. symbol parameter min. max. units t d(fsc) frame sync (fsc) delay time - t wl 100 ns t su(fsc) frame sync (fsc) set-up time 60 - ns t wfh frame sync (fsc) high time pulse width 130 - ns t dck data clock (dck) period 440 (1) - ns t wh data clock (dck) high time pulse width 150 - ns t wl data clock (dck) low time pulse width 150 - ns t d(dc) output data (do) to data clock delay time - 100 (2) ns t su(d) input data (di) set-up time 60 - ns t h(d) input data (di) hold time 60 - ns handbook, full pagewidth fsc dck di/do fsc dck do b7 b7 b6 di b2 b1 b0 b5 b4 b3 b6 b7 t w(fh) t dck t su(fsc) t h(d) t su(d) t wh t wl t d(fsc) t d(dc) mgm795 fig.32 4-wire interface timing in speech mode.
2001 apr 17 71 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 16 external i/o interfaces 16.1 external analog interfaces 16.1.1 g eneral purpose adc and dac for general use, for instance battery management, parallel set detection or speaker amplifier volume control, a 2-line multiplexed 8-bit adc and an 8-bit dac are on-chip. the adc and the dac consist of several analog sub-blocks called avs and aad, which are controlled by the digital block dca (see fig.33). block avs generates voltages in a time multiplexed way, and acts as a dac with the bandgap voltage v bgp as input voltage. block aad contains a comparator that is part of the successive approximation adc formed by a combination of avs, aad and dca. the analog-to-digital conversion can be performed on two external input signals: ad0in and ad1in. the whole circuit is active as long as the chip is in system-on mode. both the adc and the dac can be controlled by the microcontroller, the sfr mapped dca block allowing the user a flexible interface to analog peripherals. 16.1.2 g eneral purpose adc the on-chip adc is a two channel multiplexed 8-bit converter. the control of this converter is done via two bits in the microcontroller gpadc sfr. one bit selects the channel and the other bit is the converter request bit. the request bit is reset by hardware when the converter has finished its conversion cycle. the adc (aad in fig.33), is of the successive approximation type. an internal register contains the value of the slider position and is changed after each comparison of v adc with one of the two possible analog-to-digital inputs (ad0in and ad1in). after 8 comparisons the conversion is finished and the contents of the internal register is copied into the register gpadr. total analog-to-digital conversion time (from setting the request bit until gpadr ready) is less than 50 ms. this register can in turn be read by the internal microcontroller. 16.1.2.1 general purpose adc register (gpadc) table 64 general purpose adc register (sfr address c3h); reset state 00h table 65 description of gpadc bits 16.1.2.2 general purpose adc result register (gpadr) this register holds the 8-bit result value from the conversion. the conversion range is 0 to 2000 mv (v ref ) with 8 mv resolution. table 66 general purpose adc result register (sfr address c2h); reset state 00h, read only 76543210 ----- aadc cs reqcom bit symbol description 7to3 - these 5 bits are reserved. 2 aadc automatic analog-to-digital conversion. if aadc = 1, then a conversion is performed every 30 ms, regardless of state of request confirm bit. 1cs channel select. if cs = 0, analog-to-digital conversion input is on pin ad0in. if cs = 1, analog-to-digital conversion input is on pin ad1in. switching of the analog-to-digital channel is only allowed when no analog-to-digital conversion currently is in progress. otherwise the resulting value will be corrupt. 0 reqcom request con?rm. 76543210 a/d.7 a/d.6 a/d.5 a/d.4 a/d.3 a/d.2 a/d.1 a/d.0
2001 apr 17 72 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 16.1.3 g eneral purpose dac the on-chip dac is a single channel 8-bit converter. the control of this converter is done via the gpdar register. the value written in this register triggers the conversion which will be present at the output pin after the digital-to-analog conversion cycle (<25 m s). the range from the digital-to-analog output is 0 to 2000 mv (v ref ). the conversion principle for both analog-to-digital and digital-to-analog conversion is shown in fig.34. 16.1.3.1 general purpose dac register (gpdar) table 67 general purpose dc a register (sfr address c4h); reset state 80h 76543210 d/a.7 d/a.6 d/a.5 d/a.4 d/a.3 d/a.2 d/a.1 d/a.0 handbook, full pagewidth mgm796 v acm r dac v adc avs aad symod.4 (mic supply bit) v mic v ref daout ad0in ad1in vrefr dca gpadc gpdar gpadr gpadc (channel request bit) v bgp fig.33 the architecture of the auxiliary dac and adc. handbook, full pagewidth mgm797 time pin gpdar represents output gpadc sfr has been changed by the microcontroller gpadc sfr has been changed by the micro hw resets request bit. conversion finished. result in gpadr sfr conversion cycle ( < 30 m s) analog-to-digital conversion conversion cycle ( < 10 m s) digital-to-analog conversion fig.34 analog-to-digital and digital-to-analog conversion principle.
2001 apr 17 73 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 16.2 external digital interfaces for control of peripherals like a display, ringer, key pad and line interface a large number of general purpose digital i/o pins are available in addition to the flash memory, lcd control pins and msk or iom modem pins. the exact number of free i/o pins depends on the choice of peripherals that make up the system configuration. in case all alternative port functions of p1 and p3 are used, 10 input lines remain available on p1 and p3 of which 7 are programmable for interrupts. i/o ports p1 and p3 are weak pull-up types which can therefore be used either as inputs or outputs. the reset value of p1 and p3 is ffh (input mode). in output mode for driving with a logic 1 (weak pull-up) the external load of p1 and p3 should be equivalent to >100 k w , for driving with a logic 0 the sink current should not exceed 4 ma. in addition to p1 and p3 there are 16 output ports available at p2 and ma. output ports p2 and ma are push-pull ports and their reset value is 00h (output 00h). the driving level of p2 and ma is 4 ma for either logic 0 or logic 1. port p4 provides the flash memory and display control signals. the p1, p3 and p4 i/o lines are available as sfr bit-addressable i/o registers in the configuration shown in fig.35, while p2 and ma are available as (not bit addressable) xdata mapped ports (for exact configuration and detailed description see chapter 12). the ma and p2 ports are described in chapter 12. the configuration of ports p1 and p3 are described in the tables 68 to 76. mgm798 ma0 0 ma1 1 ma2 2 ma3 3 ma4 4 ma5 5 ma6 6 ma7 7 ma p00 0 p01 1 p02 2 p03 3 p04 4 p05 5 p06 6 p07 7 p0 p1.0/ex2 0 p1.1/ex3 1 p1.2/ex4 2 p1.3/ex5 3 p1.4/ex6 4 p1.5 5 p1.6/scl 6 p1.7/sda 7 p1 p2.0 0 p2.1 1 p2.2 2 p2.3 3 p2.4 4 p2.5 5 p2.6 6 p2.7 7 p2 p3.0/mout0/do 0 p3.1/mout1/dck 1 p3.2/ex0n 2 p3.3/ex1n 3 p3.4/t0 4 p3.5/t1 5 p3.6/mout2/fsc 6 p3.7/min/di 7 p3 p4.0/le 0 p4.1/fsk 1 p4.2/fso 2 p4.3 3 p4.4/fsi 4 p4.5/gpc 5 p4 fig.35 dtam general purpose digital i/o configuration.
2001 apr 17 74 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 16.2.1 p ort 1r egister (p1) the alternative outputs (sda and scl) are connected with the general purpose outputs via an and logic gate. therefore when using the alternative functions the corresponding port bits have to be set to a logic 1. for control of i 2 c-bus peripherals like for instance eeproms and lcd displays, p1.6 and p1.7 can also be used as sda and scl to support i 2 c-bus. see section 10.11 on how to activate this alternative function of p1.6 and p1.7. the rest of port 1 is defined as general purpose i/o pins as for the standard 80c51 microcontroller. table 68 port 1 register (sfr address 90h); bit addressable; reset state ffh table 69 p1 pin con?guration 16.2.2 p ort 3r egister (p3) port 3 is defined as a set of 8 general purpose i/o pins similar to the standard 80c51 microcontroller except for p3.6 and p3.7 which do not have the rd and wr functionality (the rd and wr are separate pins). table 72 gives the different functions and the corresponding port configurations available on p3.7, p3.6, p3.1 and p3.0. the last column gives the function and configuration after reset. table 70 p3 (b0h) bit assignment; bit addressable; reset state ffh; note 1 note 1. the alternative outputs (for msk, iom) are connected with the general purpose outputs via an and logic gate. therefore when using the alternative functions the corresponding port bits have to be set to a logic 1. table 71 p3 pin con?guration table 72 port 3.7, 3.6, 3.1 and 3.0 modes and con?guration 76543210 p1.7/sda p1.6/scl p1.5 p1.4/ex6 p1.3/ex5 p1.2/ex4 p1.1/ex3 p1.0/ex2 port pins configuration p1.7 and p1.6 open-drain p1.5 to p1.0 quasi-bidirectional 76543210 p3.7/min/di p3.6/mout 2/fsc p3.5/t1 p3.4/t0 p3.3/ex1n p3.2/ex0n p3.1/mout 1/dck p3.0/mout 0/do port pins configuration p3.7, p3.6, p3.1 and p3.0 see table 72 p3.5 to p3.2 quasi-bidirectional msk iom general purpose i/o port (reset state) signal master slave mout0 push-pull do open-drain 4 ma open-drain 4 ma p3.0 quasi-bidirectional weak pull-up mout1 push-pull dck push-pull input p3.1 mout2 push-pull fsc push-pull input p3.6 min input di input input p3.7
2001 apr 17 75 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 16.2.3 p ort 4r egister (p4) the alternative outputs (gpc, fso, fsk and le) are connected with the general purpose outputs via an and gate. therefore, when using the alternative functions the corresponding port bits should be set to a logic 1. table 73 port 4 register (sfr address 98h); bit addressable; reset state 1ehh; note 1 16.2.4 p ort 4c onfiguration r egister (p4cfg) this register is used to select the output configuration of the pins wr, rd and p4.0 to p4.4. the output configuration is open-drain by default after reset. note that the output configuration of p4.5 is selected by the p4.5 bit in sfr altp. table 74 port 4 con?guration register (sfr address 9fh); reset state 00h table 75 description of p4cfg bits 16.2.5 a lternative p ort f unction r egister (altp) this register selects the pin configuration for the msk, iom master/slave and general purpose function; see table 77. the general purpose clock function is described in section 9.1. the le functionality is described in section 10.13. table 76 alternative port function register (sfr address abh); reset state 00h table 77 p3.7, p3.6, p3.1 and p3.0 selection of pin con?gurations for alternative function 76543210 -- p4.5/gpc p4.4/fsi p4.3 p4.2/fso p4.1/fsk p4.0/le 76543210 wr rd eam p4.4 p4.3 p4.2 p4.1 p4.0 bit symbol description 7 wr if wr = 0, then open-drain con?guration. if wr = 1, then push-pull con?guration. 6 rd if rd = 0, then open-drain con?guration. if rd = 1, then push-pull con?guration. 5 eam the eam bit is used to select the enhanced addressing mode; this is described in more detail in chapter 12. 4 p4.4 if p4.4 = 0, then open-drain con?guration. if p4.4 = 1, then push-pull con?guration. 3 p4.3 if p4.3 = 0, then open-drain con?guration. if p4.3 = 1, then push-pull con?guration. 2 p4.2 if p4.2 = 0, then open-drain con?guration. if p4.2 = 1, then push-pull con?guration. 1 p4.1 if p4.1 = 0, then open-drain con?guration. if p4.1 = 1, then push-pull con?guration. 0 p4.0 if p4.0 = 0, then open-drain con?guration. if p4.0 = 1, then push-pull con?guration. 76543210 - iom on p3 iom master/ msk p4.5 gpc off/on gpc source le off/on early le altp.6 altp.5 mode 0 0 general purpose i/o port 0 1 msk 1 0 iom slave 1 1 iom master
2001 apr 17 76 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 17 electrical characteristics 17.1 limiting values in accordance with the absolute maximum rating system (iec 60134); note 1 note 1. parameters are valid over operating temperature range unless otherwise specified; all voltages are with respect to v ss unless otherwise specified. symbol parameter min. max. unit v dd3v supply voltage 3.0 v (v dd3v2 and v dd3v3 ) - 0.5 +3.6 v v dd2.5v supply voltage 2.5 v (v dd3v1 , v dda , v ddpll ) - 0.5 +3.3 v v i input voltage on any pin with respect to ground (v ss ) - 0.5 v dd + 0.5 v i i/o maximum sink/source current for all input/output pins - 10 +10 ma i vdd , i vss maximum dc current for each supply pin - 150 ma p tot total power dissipation - 800 mw v esd(hbm) maximum esd stress level applied; according to human body model (100 pf; 1.5 k w ) - 1500 v v esd(mm) maximum esd stress level applied; according to machine model (200 pf; 0.75 m h) - 150 v t amb operating ambient temperature - 25 +70 c t stg storage temperature - 65 +150 c
2001 apr 17 77 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 17.2 supply characteristics notes 1. this defines requirements for the external power-on reset circuit. the exact requirements can be relaxed depending on the specific application. a hysteresis is required to overcome reset oscillations especially in battery operated applications. 2. for these parameters, the recommended external components are specified which are supported by the internal oscillator. this is not measured on a sample-by-sample basis. symbol parameter conditions/remarks min. typ. max. unit v dd3v1 digital supply voltage to pins v dd3v1 2.25 2.5 2.75 v v dd3v2/3 digital supply voltage to pins v dd3v2 and v dd3v3 voltage must be set equal or higher than v dd3v1 2.25 3.0 3.3 v v dda analog supply voltage to pin v dda 2.25 2.5 2.75 v v ddpll analog supply voltage to pin v ddpll 2.25 2.5 2.75 v i dd(max) total input current when recording a message from pstn, cas, line echo cancellation, listen in on codec2 to all supply pins pll on; codec1 and codec2 active; dsp at 42 mhz; microcontroller at 21 mhz; v dd3v1 =v dda =v ddpll = 2.75 v; v dd3v2 =v dd3v3 = 3.30 v; no load - 28 35 ma v dd3v1 only - 22.0 - ma v dd3v2 only no load on port pins - 0.01 - ma v dd3v3 only no load on port pins - 0.01 - ma v dda only - 5.0 - ma v ddpll only - 0.5 - ma i dd(pots) pots mode supply current to all supply pins pll off; dsp only generating dtmf tones; only codec1 d/a on; microcontroller in power-down; xtal runs at 3.58 mhz; pmtr2.0 = 1; cdtr2.0 = 1; v dd3vx =v dda =v ddpll = 2.25 v; no load - 2.6 3.5 ma i dd(sys-off) total input current when in system-off mode digital-to-analog part of codec1 and codec2 switched-off - 0.17 0.90 ma por (power-on reset) v th(h) por threshold value high note 1 -- 2.2 v v th(l) por threshold value low note 1 1.8 -- v v hys por hysteresis note 1 0.08 -- v osc c l(xtal1,2) crystal load capacitances at xtal1 and xtal2 to v ss 3.45 to 13.824 mhz; note 2 - 18 39 pf r s crystal series resistance 3.58 mhz; note 2 -- 300 w 13.824 mhz; note 2 -- 40 w c p crystal shunt capacitance note 2 -- 7pf
2001 apr 17 78 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 17.3 digital i/o notes 1. v dd(periph) refers to the peripheral supplies v dd3v2 and v dd3v3 . 2. v dd - vout = 400 mv (for i oh ), vout - v ss = 400 mv (for | i ol | ). 3. 4 ma drive levels are only guaranteed for v dd3v2/3 greater than 2.7 v. 4. on a low-to-high transition, the output current value will be 4 ma for one microcontroller clock period, before changing to the specified lower value. v dd3vx =v dda =v ddpll = 2.75 v. 5. if the msk mode is activated, the output current value for p3.0, p3.1 and p3.6 will continuously be 4 ma. if the iom master mode is activated, the output current value for p3.1 and p3.6 will continuously be 4 ma. 6. when configured as push-pull. symbol parameter conditions min. max. unit v il low-level input voltage sda and scl 0 0.3v dd3v1 v other pins note 1 0 0.2v dd(periph) v v ih high-level input voltage sda and scl 0.7v dd3v1 v dd(periph) v other pins note 1 0.8v dd(periph) v dd(periph) v | i ol | low-level output current notes 2 and 3 rd, wr, psen, p0, p1, p2, p3, p4 and ma 4 - ma i oh high-level output current notes 2 and 3 rd (6) , wr (6) , psen, p0, p2, p4 (6) and ma - ma p1.0, p1.1, p1.2, p1.3, p1.4, p1.5 and p3 90 (4)(5) 250 (4)(5) m a i load total static load current on v dd3v2 /v dd3v3 - 30 ma
2001 apr 17 79 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 17.4 analog supplies and general purpose adc and dac notes 1. v bgp output current is zero. decoupling capacitance between v bgp and v ssa is 100 nf. 2. the v ref output current is zero however the v ref output buffer is loaded via v mic (see note 3). decoupling capacitance between v ref and v ssa is between 1 and 100 m f, with a 100 nf capacitance in parallel. the output can only source current (i.e. not sink). 3. pin v mic is connected to v ref via an internal switch. the v mic switch is closed by setting symod.4 = 1. the v mic dc output current is max. 400 m a, and v ref must be programmed to its typical value. for the connections of v mic to a microphone (see fig.36). v mic adjustment can only be done by adjusting v ref . 4. output resistances represent the theoretical maximum which can be guaranteed by design. actual output resistance values can vary depending on several conditions as processing, temperature and drive signal shape. symbol parameter conditions min. typ. max. unit v bgp avr bandgap voltage note 1 1.15 1.23 1.30 v v ref(reset) reference voltage, after reset note 2 1.9 2.0 2.1 v v ref(tuned) reference voltage when tuned via vrefr - 30 - mv dv mic v ref - v mic note 3 - 40 - mv v adin,ofs adin1 and adin2 input offset voltage - 20 50 mv v adin1,2 adin1 and adin2 input voltage range 0 - v ref mv r adin1,2 adin1 and adin2 input resistance 210 - m w r daout daout output resistance note 4 - 7 - k w v daout daout output voltage range 8 - v ref mv
2001 apr 17 80 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 17.5 codecs for all values speci?ed, v ref is tuned to 2.0 v; unless mentioned differently, typical values for the analog-to-digital and digital-to-analog ?lter characteristics conform to the g.712 speci?cation. symbol parameter conditions min. typ. max. unit analog-to-digital path performance v mic maximum microphone input level notes 1 and 2 --- 8 dbm r mic(dm) microphone input resistance from micm to micp, differential mode notes 3 and 4 - 250 - k w r mic(cm) microphone input resistance from micm to v ssa or micp to v dda , common mode notes 3 and 5 - 25 - k w v lifin(max) maximum line input level notes 1 and 6 --- 8 dbm r lifin1(dif) line input resistance from lifmin1 to lifpin, differential mode notes 3 and 7 - 1000 - k w r lifin1(cm) minimum line input resistance from lifmin1 to vssa or lifpin to v dda , common mode notes 3 and 8 - 25 - k w r lifin2(dif) minimum line input resistance from lifmin2 to lifpin, differential mode notes 3 and 9 - 50 - k w r lifin2(cm) minimum line input resistance from lifmin2 to v ssa , common mode notes 3 and 10 - 1000 - k w g (a/d)(7db) typical analog-to-digital path gain of codec1/ codec2 from lif/mic to dr1/dr2 notes 1 and 11 - 7.1 - db g (a/d)(23db) notes 1 and 12 - 23.5 - db g (a/d)(35db) notes 1 and 13 - 35.5 - db g (a/d)(preamp) additional path gain for codec2 microphone preampli?er notes 1 and 14 - 14.5 - db d g (a/d)(7db/23db) delta analog-to-digital path gain of codec1/ codec2 from lif/mic to dr1/dr2 notes 1 and 15 - 101db d g (a/d)(35db) notes 1 and 16 - 1.5 0 1.5 db f (a/d)(idle) analog-to-digital idle channel noise notes 1 and 17 -- 85 - 75 dbm0p s/(n+thd) (a/d)( - 25) analog-to-digital signal-to-(noise + total harmonic distortion) ratio for codec2 at 23 db gain notes 1 and 18 - 76 - dbp s/(n+thd) (a/d)( - 49) notes 1 and 19 40 52 - dbp s/(n+thd) (a/d)( - 65) notes 1 and 20 - 36 - dbp s/(n+thd) (a/d)( - 9) analog-to-digital signal-to-(noise + total harmonic distortion) ratio for codec1 at 7 db gain notes 1 and 21 - 78 - dbp s/(n+thd) (a/d)( - 25) notes 1 and 22 - 62 - dbp s/(n+thd) (a/d)( - 49) notes 1 and 23 24 38 - dbp t d(g)(a/d) analog-to-digital path group delay - 500 -m s digital-to-analog path performance v lifout(dif) maximum line interface differential output level note 24 - 1400 - mv r lifout line interface output resistance note 25 - 20 -w v spkrd maximum speaker differential output level note 26 - 1400 - mv r spkr speaker output resistance note 25 - 8 -w
2001 apr 17 81 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 notes 1. for the definition of the amplitude units (db, dbm, dbm0, dbmp, dbm0p) see section 13.1. all measurements are performed with chopping switched on (pmtr2 = 04h) and unless mentioned otherwise, all measurements are performed in rtc mode = 0 (ckcon.6 = 0) and at nominal supply voltage (v dda = 2.50 v). 2. maximum sinewave rms level applied differentially between pins micp and micm. the analog-to-digital path gain for codec2 is set to 7 db (dtcon.1 = 1, dtcon.2 = 0). for larger input levels the output signal will saturate. for higher analog-to-digital gain settings (including the microphone preamplifier), the maximum rms input level will decrease by the same amount as the gain will increase. 3. all input resistances represent the theoretical minimum which can be guaranteed by design. note that given input resistance values can vary depending on several conditions as processing, temperature and input signal shape. for the measurement, the input signal is a 1 khz sine wave which is ac coupled with a 1 m f capacitor (see application example in fig. 36). the input resistance will increase when others than the noted gains are selected. for detailed information on input resistances for all gain settings, refer to the pcd6003 application note which is available. 4. the differential resistance is seen between pins micp and micm. the minimum resistance will be seen for an analog-to-digital path gain of 7 db and will slightly increase for all other gain settings. 5. the common mode resistance is seen between micp/micm and v ssa . micp and micm are shorted. it corresponds to rmicvdd ||rmicvss (see fig.36). the minimum resistance will be seen for an analog-to-digital path gain of 23/35 db and will increase for all other gain settings. 6. maximum sinewave rms level applied differentially between pins lifpin and lifmin1/lifmin2. v ref is tuned to 2.0 v and the analog-to-digital path gain for codec1 is set to 7 db (cdvc1.3 = 0, dtcon.5 = 0). for larger input levels the output signal will saturate. for higher analog-to-digital gain settings, the maximum rms input level will decrease by the same amount as the gain will increase. 7. the differential resistance is seen between pins lifpin and lifmin1. the minimum resistance will be seen for an analog-to-digital path gain of 23/35 db and will increase for other gain settings. 8. the common mode resistance is seen between lifpin/lifmin1 and v ssa . lifpin and lifmin1 are shorted. it corresponds to r lif1vdd || r lif1vss (see fig.36). the minimum resistance will be seen for an analog-to-digital path gain of 7 db and will increase for other gain settings. 9. the differential resistance is seen between pins lifpin and lifmin2. the minimum resistance will be seen for an analog-to-digital path gain of 23/35 db and will increase for other gain settings. 10. the common mode resistance is seen between lifpin/lifmin2 and v ssa . lifpin and lifmin2 are shorted. it corresponds to r lif2vdd || r lif2vss (see fig. 36). the minimum resistance will be seen for an analog-to-digital path gain of 7 db and will increase for other gain settings. 11. absolute typical gain for codec1 and codec2 for gain step 7db (cdvc1.3 = 0, dtcon.5 = 0 and dtcon.1 = 1), measured at the dr1/dr2 bitstream interface as defined in fig.29 using a 1020 hz sinewave. v ref is tuned to 2.00 v. 12. absolute typical gain for codec1 and codec2 for gain step 23 db (cdvc1.3 = 1, cdvc2.3 = 0 and dtcon.5 = 0, dtcon.1 = 0), measured at the dr1/dr2 bitstream interface as defined in fig.29 using a 1020 hz sinewave. v ref is tuned to 2.00 v. d g(d/a) delta digital-to-analog path gain from dt1/dt2 to spkr or lifout notes 1 and 27 - 101db f (d/a)(idle) digital-to-analog idle channel noise notes 1 and 28 -- 89 - 80 dbmp s/(n+thd) (d/a)(0) digital-to-analog signal-to-(noise + total harmonic distortion) ratio notes 1 and 29 - 80 - dbp s/(n+thd) (d/a)( - 40) notes 1 and 30 - 42 50 - dbp t d(g)(d/a) digital-to-analog path group delay - 500 -m s symbol parameter conditions min. typ. max. unit
2001 apr 17 82 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 13. absolute typical gain for codec1 and codec2 for gain step 35 db (cdvc2.3 = 1, dtcon.5 = 1 and dtcon.1 = 0), measured at the dr1/dr2 bitstream interface as defined in fig.29 using a 1020 hz sinewave. v ref is tuned to 2.00 v. 14. absolute typical additional gain for codec2 when enabling the 15 db microphone preamplifier (dtcon.1 = 0 and dtcon.2 = 1), measured using a 1020 hz sinewave. v ref is tuned to 2.00 v. 15. the deviation of the actual gain for codec1 and codec2 from the specified absolute typical gain for gain steps 7 db and +23 db (cdvc2.3 = 0 and dtcon.5 = 0), measured at the dr1/dr2 bitstream interface as defined in fig.29 using a 1020 hz sinewave. including eventual gain variation for codec2 when enabling the microphone preamplifier. 16. the deviation of the actual gain for codec1 and codec2 from the specified absolute typical gain for gain step 35 db (cdvc2.3 = 1, dtcon.5 = 1 and dtcon.1 = 0), measured at the dr1/dr2 bitstream interface as defined in fig.29 using a 1020 hz sinewave. v ref is tuned to 2.00 v. including eventual gain variation for codec2 when enabling the microphone preamplifier. 17. the analog-to-digital path gain is set to 7 db for codec1 and to 23 db for codec2 (cdvc1.3 = 0, cdvc2.3 = 0, dtcon.5 = 0, dtcon.1 = 0 and dtcon.2 = 0). lifpin and lifmin1 or lifmin2 are shorted together for codec1, micp and micm are shorted together for codec2. the measured value is psophometrically weighted. 18. the analog-to-digital path gain is set to 23 db for codec2 (cdvc2.3 = 0, dtcon.1 = 0 and dtcon.2 = 0), when a sinewave of 1020 hz with a level of - 25 dbm is applied between micp and micm. the value includes harmonic distortion and is psophometrically weighted. 19. the analog-to-digital path gain is set to 23 db for codec2 (cdvc2.3 = 0, dtcon.1 = 0 and dtcon.2 = 0), when a sinewave of 1020 hz with a level of - 49 dbm is applied between micp and micm. the value includes harmonic distortion and is psophometrically weighted. 20. the analog-to-digital path gain is set to 23 db for codec2 (cdvc2.3 = 0, dtcon.1 = 0 and dtcon.2 = 0), when a sinewave of 1020 hz with a level of - 65 dbm is applied between micp and micm. the value includes harmonic distortion and is psophometrically weighted. 21. the analog-to-digital path gain is set to 7 db for codec1 (cdvc1.3 = 0 and dtcon.5 = 0), when a sinewave of 1020 hz with a level of - 9 dbm is applied between lifpin and lifmin1 or lifmin2. the value includes harmonic distortion and is psophometrically weighted. 22. the analog-to-digital path gain is set to 7 db for codec1 (cdvc1.3 = 0 and dtcon.5 = 0), when a sinewave of 1020 hz with a level of - 25 dbm is applied between lifpin and lifmin1 or lifmin2. the value includes harmonic distortion and is psophometrically weighted. 23. the analog-to-digital path gain is set to 7 db for codec1 (cdvc1.3 = 0 and dtcon.5 = 0), when a sinewave of 1020 hz with a level of - 49 dbm is applied between lifpin and lifmin1 or lifmin2. the value includes harmonic distortion and is psophometrically weighted. 24. sinewave rms level measured differentially between pins lifpout and lifmout. the digital-to-analog path gain is set to 6 db (cdvc1.7 = 1 and cdvc1.6 = 1). the input signal is 1020 hz with the maximum level of 3.14 dbm0 at the pcm interface (see section 13.1 for definitions). load resistance is greater than 400 w . lower load resistances will cause harmonic distortion greater than 1% at the line output. 25. all output resistances represent the theoretical maximum which can be guaranteed by design at maximum signal strength (as defined in note 24). actual output resistance values can vary depending on several conditions as processing, temperature and drive signal shape. for smaller signals the output resistance will strongly decrease. 26. sinewave rms level measured differentially between pins spkrp and spkrm. the digital-to-analog path gain is set to 6 db (cdvc2.7 = 1 and cdvc2.6 = 1). the input signal is 1020 hz with the maximum level of 3.14 dbm0 at the pcm interface (see section 13.1 for definitions). load resistance is greater than 100 w . lower load resistances will cause harmonic distortion greater than 1% at the speaker output. 27. the deviation of the actual digital-to-analog gain from the nominal digital-to-analog gain as specified in cdvc1/cdvc2, measured at the dt1/dt2 bitstream interface as defined in using a 1020 hz sinewave. v ref is tuned to 2.00 v.
2001 apr 17 83 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 28. the digital-to-analog path gain for codec1 and codec2 is set to 0 db (cdvc1/2 = 8xh). the dsp is in idle mode. the value is differentially measured and psophometrically weighted. 29. the digital-to-analog path gain in control register cdvc1/2 = 8xh is set to 0 db for codec1 and codec2, when a bit stream representing a sinewave of 970 hz with a level of 0 dbm0 is applied at the pcm interface (dsp output). the value includes harmonic distortion and is psophometrically weighted. the load between spkrm and spkrp or lifmout and lifpout is 100 pf in parallel to 150 w and 800 mh. 30. the digital-to-analog path gain in control register cdvc1/2 = 8xh is set to 0 db for codec1 and codec2, when a bit stream representing a sinewave of 970 hz with a level of - 40 dbm0 is applied at the pcm interface (dsp output). the value includes harmonic distortion and is psophometrically weighted. the load between spkrm and spkrp or lifmout and lifpout is 100 pf in parallel to 150 w and 800 mh.
2001 apr 17 84 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 18 application diagrams handbook, full pagewidth mgt444 200 k w 100 k w 100 k w 200 k w 100 nf 100 nf 47 m f 1 m f 47 m f 68 m f 10 m f 100 nf 100 nf 100 nf (1) (1) (1) 100 nf 100 nf 100 nf 100 nf 10 nf 100 nf 100 nf v dd 1/2v dd 1/2v dd pstn b pstn a lifmin1 lifmin2 lifpin v dd3v1 v dd3v2 codec1 codec2 v dd3v3 - 6 db 10 m f 100 nf 10 m f 100 nf 2.2 m f 100 nf 7 db 23 db 35 db d 7 db 23 db 35 db d line interface receive output r lifxvxd r lifxmd r lifxvss r micvdd r micvss r micdm 100 w 2 k w 100 k w 100 k w 100 w 5 w 0 db 15 db micp v mic micm handsfree microphone handset microphone line interface v bgp v ref v ddpll v dd r x v dd v dda v dd fig.36 application example: supply and analog input connections for line interface, caller id and handsfree. (1) the decoupling capacitors for v dd3v1 , v dd3v2 and v dd3v3 must be mounted as close as possible to the respective pins.
2001 apr 17 85 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 handbook, full pagewidth mbl279 keyboard display flash speech memory dtam pcd6003 pstn codec2 codec1 line interface a fig.37 stand alone digital answering machine with handsfree application example. handbook, full pagewidth mbl280 keyboard display flash speech memory dtam pcd6003 pstn codec2 codec1 line interface a fig.38 digital telephone answering machine with handsfree application example.
2001 apr 17 86 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 handbook, full pagewidth mbl281 keyboard display flash speech memory ct0/1 radio dtam pcd6003 pstn codec2 codec1 line interface a fig.39 analog cordless base station with digital handsfree answering machine application example. handbook, full pagewidth mbl282 keyboard display flash speech memory dtam pcd6003 codec2 a fig.40 portable voice memo recorder application example.
2001 apr 17 87 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 handbook, full pagewidth mbl283 serial or parallel interface to host controller flash speech memory dtam shared with car radio pcd6003 codec2 a fig.41 automotive application example (audible car status information is presented to the driver).
2001 apr 17 88 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 19 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 2.90 2.65 0.25 0.45 0.30 0.25 0.14 14.1 13.9 0.8 1.95 18.2 17.6 1.2 0.8 7 0 o o 0.2 0.2 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.6 sot318-2 mo-112 d (1) (1) (1) 20.1 19.9 h d 24.2 23.6 e z 1.0 0.6 d b p e q e a 1 a l p detail x l (a ) 3 b 24 c b p e h a 2 d z d a z e e v m a 1 80 65 64 41 40 25 pin 1 index x y d h v m b w m w m 97-08-01 99-12-27 0 5 10 mm scale qfp80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm sot318-2 a max. 3.2
2001 apr 17 89 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 20 soldering 20.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. 20.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. 20.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 20.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2001 apr 17 90 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 20.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, lfbga, sqfp, tfbga not suitable suitable hbcc, hlqfp, hsqfp, hsop, htqfp, htssop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable
2001 apr 17 91 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 21 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. data sheet status (1) product status (2) definitions objective data development this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. preliminary data quali?cation this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. product data production this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change noti?cation (cpcn) procedure snw-sq-650a. 22 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 23 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2001 apr 17 92 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 24 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
2001 apr 17 93 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 notes
2001 apr 17 94 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 notes
2001 apr 17 95 philips semiconductors product speci?cation digital telephone answering machine chip pcd6003 notes
? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 2001 72 philips semiconductors C a worldwide company for all other countries apply to: philips semiconductors, marketing communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 3 figtree drive, homebush, nsw 2140, tel. +61 2 9704 8141, fax. +61 2 9704 8139 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 7 - 9 rue du mont valrien, bp317, 92156 suresnes cedex, tel. +33 1 4728 6600, fax. +33 1 4728 6638 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: philips hungary ltd., h-1119 budapest, fehervari ut 84/a, tel: +36 1 382 1700, fax: +36 1 382 1800 india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, via casati, 23 - 20052 monza (mi), tel. +39 039 203 6838, fax +39 039 203 6800 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland : al.jerozolimskie 195 b, 02-222 warsaw, tel. +48 22 5710 000, fax. +48 22 5710 001 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 5f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2451, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 60/14 moo 11, bangna trad road km. 3, bagna, bangkok 10260, tel. +66 2 361 7910, fax. +66 2 398 3447 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 208 730 5000, fax. +44 208 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 3341 299, fax.+381 11 3342 553 printed in the netherlands 403506/02/pp 96 date of release: 2001 apr 17 document order number: 9397 750 08242

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